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PDF CAT5409 Data sheet ( Hoja de datos )
| Número de pieza | CAT5409 | |
| Descripción | Quad Digitally Programmable Potentiometers (DPP) | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT5409 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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CAT5409
Quad Digitally Programmable Potentiometers
(DPP™) with 64 Taps and I²C Interface
FEATURES
Four linear taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
I²C interface
Low wiper resistance, typically 80Ω
Four non-volatile wiper settings for each
potentiometer
Recall of saved wiper settings at power-up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Write protection for data register
For Ordering Information details, see page 15.
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
DESCRIPTION
The CAT5409 is four Digitally Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP.
Associated with each wiper control register are four
6-bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data
registers is via a I²C serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The Write Protection (¯W¯P¯) pin protects against
inadvertent programming of the data register.
The CAT5409 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
FUNCTIONAL DIAGRAM
RH0
RH1
RH2
RH3
SDA 1
A1 2
RL1 3
RH1 4
RW1 5
GND 6
NC 7
RW2 8
RH2 9
RL2 10
SCL 11
A3 12
24 WP
23 A2
22 RW0
21 RH0
20 RL0
19 VCC
18 NC
17 RL3
16 RH3
15 RW3
14 A0
13 NC
VCC 1
RL0 2
RH0 3
RW0 4
A2 5
WP 6
SDA 7
A1 8
RL1 9
RH1 10
RW1 11
GND 12
24 NC
23 RL3
22 RH3
21 RW3
20 A0
19 NC
18 A3
17 SCL
16 RL2
15 RH2
14 RW2
13 NC
SCL
SDA
WP
A0
A1
A2
A3
I²C BUS
INTERFACE
WIPER CONTROL
REGISTERS
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2
RL3
RW0
RW1
RW2
RW3
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2010 Rev. K
1 page  
www.DataCShAeetT4U5.c4om09
WRITE CYCLE LIMITS
Symbol Parameter
tWR Write Cycle Time
Max
5
Units
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1) (2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
V
mA
Figure 1. Bus Timing
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
tAA tDH
SDA OUT
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
SDA
SCL
START CONDITION
STOP CONDITION
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2010 Rev. K
5 Page 
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
SCL
SDA
Voltage Out
RW
www.DataCShAeetT4U5.c4om09
tWRID
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
0
1
0
1
A3
A2
A1
A0
C
K
1
0
0
1
R
0
0
P1
P0
C
K
7
0
6
0
5
4
3
2
1
0
C
K
T
O
P
T
Write Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
0
1
0
1
A3
A2
A1
A0
C
K
1
0
1
0
R
0
0
P1
P0
C
K
7
0
6
0
5
4
3
2
1
0
C
K
T
O
P
T
Read Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
R
0
1
0
1
A3
A2
A1
A0
C
K
1
0
1
1
R1
R0
P1
P0
C
K
7
0
6
0
5
4
3
2
1
0
C
K
T
O
P
T
Write Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
R
0
1
0
1
A3
A2
A1
A0
C
K
1
1
0
0
R1
R0
P1
P0
C
K
7
0
6
0
5
4
3
2
1
0
C
K
T
O
P
T
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-2010 Rev. K
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CAT5409.PDF ] | |
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