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PDF FM25H20 Data sheet ( Hoja de datos )

Número de pieza FM25H20
Descripción 2Mb Serial 3V F-RAM Memory
Fabricantes Ramtron 
Logotipo Ramtron Logotipo



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No Preview Available ! FM25H20 Hoja de datos, Descripción, Manual

Pre-Production
FM25H20
2Mb Serial 3V F-RAM Memory
Features
2M bit Ferroelectric Nonvolatile RAM
Organized as 256K x 8 bits
High Endurance 100 Trillion (1014) Read/Writes
10 Year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
Up to 40 MHz Frequency
Direct Hardware Replacement for Serial Flash
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
www.DataSheet4U.com
Write Protection Scheme
Hardware Protection
Software Protection
Low Power Consumption
Low Voltage Operation 2.7V – 3.6V
Sleep Mode Current 3 µA (typ.)
Industry Standard Configurations
Industrial Temperature -40°C to +85°C
8-pin “Green”/RoHS TDFN Package
8- pin “Green”/RoHS EIAJ SOIC Package
Description
The FM25H20 is a 2-megabit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by Serial
Flash and other nonvolatile memories.
Unlike Serial Flash, the FM25H20 performs write
operations at bus speed. No write delays are incurred.
Data is written to the memory array immediately
after it has been transferred to the device. The next
bus cycle may commence without the need for data
polling. The product offers virtually unlimited write
endurance, orders of magnitude more endurance than
Serial Flash. Also, F-RAM exhibits lower power
consumption than Serial Flash.
These capabilities make the FM25H20 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of Serial Flash can
cause data loss.
The FM25H20 provides substantial benefits to users
of Serial Flash as a hardware drop-in replacement.
The FM25H20 uses the high-speed SPI bus, which
enhances the high-speed write capability of F-RAM
technology. Device specifications are guaranteed
over an industrial temperature range of -40°C to
+85°C.
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change the
specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Rev. 2.1
Sept. 2009
Pin Configuration
Top View
/S 1
Q2
/W 3
8
7
6
VSS 4
5
VDD
/HOLD
C
D
S
Q
W
VSS
1
2
3
4
8 VDD
7 HOLD
6C
5D
Pinout is equivalent to other SPI F-RAM devices.
Pin Name
/S
/W
/HOLD
C
D
Q
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (2.7 to 3.6V)
Ground
Ordering Information
FM25H20-DG
8-pin “Green”/RoHS TDFN
FM25H20-DGTR
8-pin “Green”/RoHS TDFN,
Tape & Reel
FM25H20-G
8-pin “Green”/RoHS EIAJ SOIC
FM25H20-GTR
8-pin “Green”/RoHS EIAJ
SOIC, Tape & Reel
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 15

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FM25H20 pdf
Power Up to First Access
The FM25H20 is not accessible for a period of time
(1 ms) after power up. Users must comply with the
timing parameter tPU, which is the minimum time
from VDD (min) to the first /S low.
Data Transfer
All data transfers to and from the FM25H20 occur in
8-bit groups. They are synchronized to the clock
signal (C), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of C. Outputs are driven from the falling edge of
C.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25H20. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name Description
WREN Set Write Enable Latch
WRDI Write Disable
RDSR Read Status Register
WRSR Write Status Register
READ Read Memory Data
WRITE Write Memory Data
SLEEP Enter Sleep Mode
Op-code
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 0011b
0000 0010b
1011 1001b
FM25H20 - 2MwbwSwP.DIatFaSRheAetM4U.com
WREN - Set Write Enable Latch
The FM25H20 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit – only
the WREN op-code can set this bit. The WEL bit will
be automatically cleared on the rising edge of /S
following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or
the F-RAM array without another WREN command.
Figure 5 below illustrates the WREN command bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
Status Register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
S
01 2 3 4 5 6 7
C
D 0 0 0 0 01 1 0
Q Hi-Z
Figure 5. WREN Bus Configuration
Rev. 2.1
Sept. 2009
Page 5 of 15

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FM25H20 arduino
AC Parameters (TA = -40°C to + 85°C, VDD = 2.7V to 3.6V, CL = 30pF)
Symbol Parameter
Min
fCK C Clock Frequency
tCH Clock High Time
tCL Clock Low Time
tSU Chip Select Setup
tSH Chip Select Hold
tOD Output Disable Time
tODV Output Data Valid Time
tOH Output Hold Time
tD Deselect Time
tR Data In Rise Time
tF Data In Fall Time
tSU Data Setup Time
tH Data Hold Time
tHS /HOLD Setup Time
tHH /HOLD Hold Time
tHZ /HOLD Low to Hi-Z
tLZ /HOLD High to Data Active
0
11
11
10
10
0
40
5
5
10
10
Notes
1. tCH + tCL = 1/fCK.
2. This parameter is characterized but not 100% tested.
3. Rise and fall times measured between 10% and 90% of waveform.
FM25H20 - 2MwbwSwP.DIatFaSRheAetM4U.com
Max Units Notes
40 MHz
ns 1
ns 1
ns
ns
12 ns 2
9
ns
ns
50 ns 2,3
50 ns 2,3
ns
ns
ns
ns
20 ns 2
20 ns 2
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
10% and 90% of VDD
3 ns
0.5 VDD
30 pF
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol Parameter
CO Output Capacitance (Q)
CI Input Capacitance
Notes
1. This parameter is characterized and not 100% tested.
Min Max Units Notes
- 8 pF 1
- 6 pF 1
Data Retention (TA = -40°C to +85°C)
Symbol Parameter
TDR Data Retention
Min
Units
Notes
10 Years
Rev. 2.1
Sept. 2009
Page 11 of 15

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