DataSheet.es    


PDF PCA9541A Data sheet ( Hoja de datos )

Número de pieza PCA9541A
Descripción 2-to-1 I2C-bus master selector
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



Hay una vista previa y un enlace de descarga de PCA9541A (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! PCA9541A Hoja de datos, Descripción, Manual

www.DataSheet4U.com
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Rev. 03 — 16 July 2009
Product data sheet
1. General description
The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual
master I2C-bus applications where system operation is required, even when one master
fails or the controller card is removed for maintenance. The two masters (for example,
primary and back-up) are located on separate I2C-buses that connect to the same
downstream I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master
and are used to select one master at a time. Either master at any time can gain control of
the slave devices if the other master is disabled or removed from the system. The failed
master is isolated from the system and will not affect communication between the on-line
master and the slave devices on the downstream I2C-bus.
Two versions are offered for different architectures. PCA9541A/01 with channel 0 selected
at start-up, and PCA9541A/03 with no channel selected after start-up.
The interrupt outputs are used to provide an indication of which master has control of the
bus. One interrupt input (INT_IN) collects downstream information and propagates it to
the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let
the previous bus master know that it is not in control of the bus anymore and to indicate
the completion of the bus recovery/initialization sequence. Those interrupts can be
disabled and will not generate an interrupt if the masking option is set.
A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a
STOP condition in order to set the downstream I2C-bus devices to an initialized state
before actually switching the channel to the selected master.
An interrupt is sent to the upstream channel when the recovery/initialization procedure is
completed.
An internal bus sensor senses the downstream I2C-bus traffic and generates an interrupt
if a channel switch occurs during a non-idle bus condition. This function is enabled when
the PCA9541A recovery/initialization is not used. The interrupt signal informs the master
that an external I2C-bus recovery/initialization needs to be performed. It can be disabled
and an interrupt will not be generated.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage, which will be passed by the PCA9541A. This allows the use of
different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate
with 5 V devices without any additional protection.
The PCA9541A does not isolate the capacitive loading on either side of the device, so the
designer must take into account all trace and device capacitances on both sides of the
device, and pull-up resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O
pins are 6.0 V tolerant.

1 page




PCA9541A pdf
NXP Semiconductors
www.DataSheet4U.com
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
7. Pinning information
7.1 Pinning
PCA9541AD/01
PCA9541AD/03
INT0 1
SDA_MST0 2
16 VDD
15 INT_IN
SCL_MST0 3
14 SDA_SLAVE
RESET 4
13 SCL_SLAVE
SCL_MST1 5
12 A3
SDA_MST1 6
11 A2
INT1 7
10 A1
VSS 8
9 A0
002aae657
Fig 2. Pin configuration for SO16
INT0 1
SDA_MST0 2
SCL_MST0 3
RESET 4
SCL_MST1 5
SDA_MST1 6
INT1 7
VSS 8
PCA9541APW/01
PCA9541APW/03
16 VDD
15 INT_IN
14 SDA_SLAVE
13 SCL_SLAVE
12 A3
11 A2
10 A1
9 A0
002aae658
Fig 3. Pin configuration for TSSOP16
terminal 1
index area
SCL_MST0 1
12 SDA_SLAVE
RESET 2 PCA9541ABS/01 11 SCL_SLAVE
SCL_MST1 3 PCA9541ABS/03 10 A3
SDA_MST1 4
9 A2
Fig 4. Pin configuration for HVQFN16
Transparent top view
002aae659
PCA9541A_3
Product data sheet
Rev. 03 — 16 July 2009
© NXP B.V. 2009. All rights reserved.
5 of 41

5 Page





PCA9541A arduino
NXP Semiconductors
www.DataSheet4U.com
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Table 6. Register 0 - Interrupt Enable (IE) register bit description …continued
Legend: * default value
Bit Symbol
Access Value[1] Description
1 BUSINITMSK R/W 0*
After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT will be generated when the bus initialization is done.
Remark: Channel switching is done after bus initialization completed.
1 After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT will not be generated when the bus initialization is done
(masked).
Remark: Channel switching is done after bus initialization completed.
0 INTINMSK
R/W 0*
Interrupt on INT_IN will generate an interrupt on INT.
1 Interrupt on INT_IN will not generate an interrupt on INT (masked)
[1] Default values are the same for PCA9541A/01, PCA9541A/03.
8.3.2 Register 1: Control Register (B1:B0 = 01b)
The Control Register described below is identical for both the masters. Nevertheless,
there are physically 2 internal Control Registers, one for each upstream channel. When
master 0 reads/writes in this register, the internal Control Register 0 will be accessed.
When master 1 reads/writes in this register, the internal Control Register 1 will be
accessed.
Table 7. Register 1 - Control Register (B1:B0 = 01b) bit allocation
76543
NTESTON TESTON
0
BUSINIT
NBUSON
2
BUSON
1
NMYBUS
0
MYBUS
Table 8. Register 1 - Control Register (B1:B0 = 01b) bit description
Legend: * default value
Bit Symbol
Access Value[1]
Description
7 NTESTON R/W 0*
A logic level HIGH to the INT line of the other channel is sent (interrupt
cleared).
1 A logic level LOW to the INT line of the other channel is sent (interrupt
generated).
6 TESTON R/W 0*
A logic level HIGH to the INT line is sent (interrupt cleared).
1 A logic level LOW to the INT line is sent (interrupt generated).
5-
R only 0*
not used
4 BUSINIT R/W 0*
Bus initialization is not requested.
1 Bus initialization is requested.
3 NBUSON R only see
NBUSON bit along with BUSON bit decides whether any upstream channel
Table 11 is connected to the downstream channel or not. See Table 10, Table 11, and
Table 12.
2 BUSON
R/W see
BUSON bit along with the NBUSON bit decides whether any upstream
Table 11 channel is connected to the downstream channel or not. See Table 10,
Table 11, and Table 12.
1 NMYBUS R only see
NMYBUS bit along with MYBUS bit decides which upstream channel is
Table 11 connected to the downstream channel. See Table 9, Table 11, and Table 12.
0 MYBUS
R/W see
MYBUS bit along with the NMYBUS bit decides which upstream channel is
Table 11 connected to the downstream channel. See Table 9, Table 11, and Table 12.
[1] Default values are the same for PCA9541A/01, PCA9541A/03.
PCA9541A_3
Product data sheet
Rev. 03 — 16 July 2009
© NXP B.V. 2009. All rights reserved.
11 of 41

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet PCA9541A.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
PCA95412-to-1 I2C-bus master selectorNXP Semiconductors
NXP Semiconductors
PCA9541A2-to-1 I2C-bus master selectorNXP Semiconductors
NXP Semiconductors

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar