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PDF IDT5V9882T Data sheet ( Hoja de datos )
| Número de pieza | IDT5V9882T | |
| Descripción | 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT5V9882T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
3.3V EEPROM
PROGRAMMABLE CLOCK
GENERATOR
www.DataSheet4U.com
INDUSTRIALTEMPERATURERANGE
IDT5V9882T
FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges: 4.9kHz to 500MHz
• Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance
− Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation
capability
• I/O Standards:
− Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
− Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TSSOP package
DESCRIPTION:
The IDT5V9882T is a programmable clock generator intended for high
performance data-communications, telecommunications, consumer, and
networking applications. There are three internal PLLs, each individually
programmable, allowing for three unique non-integer-related frequencies.
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock inputs. A
glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
The IDT5V9882T can be programmed through the use of the I2C
interfaces. The programming interface enables the device to be pro-
grammed when it is in normal operation or what is commonly known as in-
system programmable. An internal EEPROM allows the user to save and
restore the configuration of the device without having to reprogram it on
power-up.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback
divider. This allows the user to generate three unique non-integer-related
frequencies. The PLL loop bandwidth is programmable to allow the user
to tailor the PLL response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to maximize jitter
attenuation. Spread spectrum generation and fractional divides are
allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
other four output banks are LVTTL. The outputs are connected to the PLLs
via the switch matrix. The switch matrix allows the user to route the PLL
outputs to any output bank. This feature can be used to simplify and optimize
the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2010 Integrated Device Technology, Inc.
1
JUNE 2010
DSC 7064/2
1 page  
IDT5V9882T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
www.DataSheet4U.com
INDUSTRIALTEMPERATURERANGE
Pre-Divider (D) Values
PLL0 1 - 255
PLL1 1 - 255
PLL2 1 - 255
Multiplier (M) Values
2 - 8190
2 - 8190
1 - 4095
Programmable Loop Bandwidth
yes
yes
yes
Spread Spectrum
Generation Capability
yes
yes
no
CRYSTAL INPUT (XTALIN/REFIN)
The crystal oscillators should be fundamental mode quartz crystals: overtone
crystals are not suitable. Crystal frequency should be specified for parallel
resonance with 50Ωmaximum equivalent series resonance.
When the XTALIN/REFIN pin is driven by a crystal, it is important to set the
internal oscillator inverter drive strength and internal tuning/load capacitor
values correctly to achieve the best clock performance. These values are
programmablethroughanI2C_MFCinterfacetoallowformaximumcompatibility
with crystals from various manufacturers, processes, performances, and
qualities. The internal load capacitors are true parallel-plate capacitors for ultra-
linear performance. Parallel-plate capacitors were chosen to reduce the
frequency shift that occurs when non-linear load capacitance interacts with load,
bias, supply, and temperature changes. External non-linear crystal load
capacitors should not be used for applications that are sensitive to absolute
frequencyrequirements.Thevalueoftheinternalloadcapacitorsaredetermined
by XTALCAP[7:0] bits, (0x07). The load capacitance can be set with a resolution
of 0.125 pF for a total crystal load range of 3.5pF to 35.4pF. Check with the
vendor's crystal load capacitance specification for the exact setting to tune the
internal load capacitor. The following equation governs how the total internal
load capacitance is set.
Where FIN is the reference frequency, M is the total feedback-divider value,
D is the pre-scaler value, P is the total post-divider value, and FOUT is the resulting
output bank frequency. The value 2 in the denominator is due to the divide-
by-2 on each of the output banks OUT2-4. Note that OUT1 does not have any
typeofpost-divider. Also,programminganyofthedividersmaycauseglitches
on the outputs.
Pre-Scaler
D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for
PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the
referenceclockwithintegervaluesrangingfrom1to255. Tomaintainlowjitter,
the divided down clock must be higher than 400KHz; it is best to use the smallest
D divider value possible. If D is set to '0x00', then this will power down the PLL
and all the outputs associated with that PLL.
XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)
Parameter
XTALCAP
Bits
8
Step Min
0.125 0
Max Units
32 pF
When using an external reference clock instead of a crystal on the XTAL/
REFIN pin, the input load capacitors may be completely bypassed. This allows
fortheinputfrequencytobeupto200MHz. Whenusinganexternalreference
clock, the XTALOUT pin must be left floating, XTALCAP must be programmed
to the default value of "0", and crystal drive strength bit, XDRV (0x06), must
be set to the default value of "11".
PRE-SCALER, FEEDBACK-DIVIDER, AND
POST-DIVIDER
Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider
which allows the user to generate three unique non-integer-related frequencies.
For output banks OUT2-OUT4, each bank has a 10-bit post-divider. The
following equation governs how the frequency on output banks OUT2-4 is
calculated.
FOUT = FIN * D ( M)
P*2
(Eq. 2)
5
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IDT5V9882T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
www.DataSheet4U.com
INDUSTRIALTEMPERATURERANGE
LOOP FILTER
TheloopfilterforeachPLLcanbeprogrammedtooptimizethejitterperformance. Thelow-passfrequencyresponseofthePLListhemechanismthatdictates
the jitter transfer characteristics. The loop bandwidth can be extracted from the jitter transfer. A narrow loop bandwidth is good for jitter attenuation while a wide
loop bandwidth is best for low jitter generation. The specific loop filter components that can be programmed are the resistor via the RZ[3:0] bits, pole capacitor
via the CZ[3:0] bits, zero capacitor via the CP[3:0] bits, and the charge pump current via the IP[2:0] bits.
The following equations govern how the loop filter is set.
VDD
From PFD
UP
DOWN
Ip
Ip
To VCO
Rz
Cp
Cz
Charge Pump and Loop Filter Configuration
Resistor (Rz) = 0.3KΩ + RZ[3:0] * 1KΩ
(Eq. 15)
Zero capacitor (Cz) = 6pF + CZ[3:0] * 27.2pF (Eq. 16)
Pole capacitor (Cp) = 1.3pF + CP[3:0] * 0.75pF (Eq. 17)
Charge pump current (Ip) = 5 * 2IP[2:0] μA
(Eq. 18)
Parameter
Bits
Step
Min
RZ 4
1 0.3
CZ 4 27.2 6
CP 4
0.75 1.3
IP 3 2n 5
Max Units
15.3 K Ω
414 pF
12.55 pF
640 μA
PLL loop filter design is beyond the scope of this datasheet. Refer to design procedures for 3-order charge-pump based PLLs. For the sake of simplicity,
the fastest and easiest way to calculate the PLL loop bandwidth (Fc) given the programmable loop filter parameters is as follows.
PLL Loop Bandwidth:
Charge pump gain (Kφ) = Ip / 2π (Eq. 19)
VCO gain (KVCO) = 950MHz/V * 2π (Eq. 20)
M = Total multiplier value (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail)
ωc = Rz * Kφ * KVCO * Cz (Eq. 21)
M * (Cz + Cp)
Fc = ωc / 2π
(Eq. 22)
Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce your
phase margin thus compromising loop stability.
11
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