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PDF KM41C16000C Data sheet ( Hoja de datos )

Número de pieza KM41C16000C
Descripción 16M x 1Bit CMOS Dynamic RAM
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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KM41C16000C, KM41V16000C
CMOS DRAM
16M x1Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 16,777,216 x 1 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5 or -6), power consumption(Normal or Low power) and
package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 16Mx1 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low
power consumption and high reliability. It may be used as main memory unit for high level computer and microcomputer.
FEATURES
Part Identification
- KM41C16000C/C-L (5V, 4K Ref.)
- KM41V16000C/C-L (3.3V, 4K Ref.)
Active Power Dissipation
Speed
-5
-6
3.3V
324
288
Unit : mW
5V
495
440
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast Parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write Operation
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
Refresh Cycles
Part
NO.
C16000C
V16000C
VCC
5V
3.3V
Refresh
cycle
4K
Refresh period
Normal L-ver
64ms 128ms
Performance Range
Speed tRAC tCAC
-5 50ns 13ns
-6 60ns 15ns
tRC
90ns
110ns
tPC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
A0-A11
A0-A11
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
16,777,216 x1
Cells
Column Decoder
Vcc
Vss
Data in
Buffer
D
Data out
Buffer
Q
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

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KM41C16000C pdf
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KM41C16000C, KM41V16000C
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Symbol
Input capacitance [D]
CIN1
Input capacitance [A0 ~ A11]
CIN2
Input capacitance [RAS, CAS, W, OE]
CIN3
Output capacitance [Q]
COUT
Min
-
-
-
-
CMOS DRAM
Max
7
5
7
7
Units
pF
pF
pF
pF
AC CHARACTERISTICS (0°CTA70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-5
Min Max
Random read or write cycle time
tRC 90
Read-modify-write cycle time
tRWC
110
Access time from RAS
tRAC
50
Access time from CAS
tCAC
13
Access time from column address
tAA
25
CAS to output in Low-Z
tCLZ
0
Output buffer turn-off delay
tOFF 0 13
Transition time (rise and fall)
tT 3 50
RAS precharge time
tRP 30
RAS pulse width
tRAS
50 10K
RAS hold time
tRSH
13
CAS hold time
tCSH
50
CAS pulse width
tCAS
13 10K
RAS to CAS delay time
tRCD 20 37
RAS to column address delay time
tRAD 15 25
CAS to RAS precharge time
tCRP
5
Row address set-up time
tASR
0
Row address hold time
tRAH
10
Column address set-up time
tASC
0
Column address hold time
tCAH
10
Column address to RAS lead time
tRAL
25
Read command set-up time
tRCS
0
Read command hold time referenced to CAS tRCH
0
Read command hold time referenced to RAS tRRH
0
Write command hold time
tWCH
10
Write command pulse width
tWP 10
Write command to RAS lead time
tRWL
13
Write command to CAS lead time
tCWL
13
-6
Min Max
110
130
60
15
30
0
0 15
3 50
40
60 10K
15
60
15 10K
20 45
15 30
5
0
10
0
10
30
0
0
0
10
10
15
15
Units Notes
ns
ns
ns 3,4,10
ns 3,5
ns 3,10
ns 3
ns 6
ns 2
ns
ns
ns
ns
ns
ns 4
ns 10
ns
ns
ns
ns
ns
ns
ns
ns 8
ns 8
ns
ns
ns
ns

5 Page





KM41C16000C arduino
KM41C16000C, KM41V16000C
READ-WRITE / READ - MODIFY - WRTIE CYCLE
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CMOS DRAM
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
D
VIL -
VIH -
Q
VIL -
tRWC
tRAS
tRP
tCRP
tRCD
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDR
COLUMN
ADDRESS
tRSH
tCAS
tCSH
tAWD
tCWD
tRWL
tCWL
tWP
tDS tDH
DATA-IN
tCLZ
tCAC
tAA
tRAC
tOFF
DATA-OUT
Dont care
Undefined

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