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PDF M24L816512SA Data sheet ( Hoja de datos )
| Número de pieza | M24L816512SA | |
| Descripción | 8-Mbit (512K x 16) Pseudo Static RAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
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ESMT
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M24L816512SA
PSRAM
8-Mbit (512K x 16)
Features
‧Advanced low-power architecture
• High speed: 55 ns, 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 2 mA @ f = 1 MHz
• Typical active current: 11 mA @ f = fMAX
• Low standby power
• Automatic power-down when deselected
Functional Description
The M24L816512SA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0through I/O15) are placed in a
high-impedance state when : deselected ( CE HIGH),
outputs are disabled ( OE HIGH), both Byte High Enable
and
Pseudo Static RAM
Byte Low Enable are disabled ( BHE , BLE HIGH), or during
a write operation ( CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip
Enable( CE LOW) and Write Enable ( WE ) input LOW. If
Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0
through I/O7) is written into the location specified on the
address pins(A0 through A18). If Byte High Enable ( BHE ) is
LOW, then data from I/O pins (I/O8 through I/O15) is written
into the location specified on the address pins (A0 through
A18).
Reading from the device is accomplished by taking Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable
( BLE ) is LOW, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High
Enable( BHE ) is LOW, then data from memory will appear on
I/O8 toI/O15. Refer to the truth table for a complete description
of read and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
1/14
1 page  
ESMT
AC Test Loads and Waveforms
www.DataSheet4U.com
M24L816512SA
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
tLZBE
tHZBE
tSK[14]
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z[11, 12]
OE HIGH to High Z[11, 12]
CE LOW to Low Z[11, 12]
CE HIGH to High Z[11, 12]
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[11, 12]
BLE / BHE HIGH to High Z[11, 12]
Address Skew
-55
Min.
Max.
55[14]
5
5
5
5
55
55
25
25
25
55
10
0
-70
Min. Max.
70
70
5
70
35
5
25
5
25
70
5
25
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V
to V CC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance
11. tHZOE, tHZCE, tHZBE, and tHZWEtransitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
5/14
5 Page 
ESMT
Package Diagrams
www.DataSheet4U.com
M24L816512SA
48-Ball (6 mm x 8mm x 1.2 mm) FBGA
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5
11/14
11 Page | ||
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