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PDF M24L816512DA Data sheet ( Hoja de datos )
| Número de pieza | M24L816512DA | |
| Descripción | 8-Mbit (512K x 16) Pseudo Static RAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
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ESMT
PSRAM
Features
‧Advanced low-power architecture
• High speed: 55 ns, 70 ns
• Wide voltage range: 2.7V to 3.6 V
• Typical active current: 2 mA @ f = 1 MHz
• Typical active current: 11 mA @ f = fMAX
• Low standby power
• Automatic power-down when deselected
Logic Block Diagram
www.DataSheet4U.com
M24L816512DA
8-Mbit (512K x 16)
Pseudo Static RAM
Functional Description
The M24L816512DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode
reducing power consumption dramatically when deselected
( CE1 LOW, CE2 HIGH or both BHE and BLE are HIGH).
The input/output pins(I/O0 through I/O15) are placed in a
high-impedance state when: deselected ( CE1 HIGH, CE2
LOW), OE is deasserted HIGH, or during a write operation
(Chip Enabled and Write Enable WE LOW). Reading from
the device is accomplished by asserting the Chip Enables
( CE1 LOW and CE2 HIGH) and Output Enable ( OE ) LOW
while forcing the Write Enable ( WE ) HIGH. If Byte Low
Enable ( BLE ) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If
Byte High Enable ( BHE ) is LOW, then data from memory will
appear on I/O8 to I/O15. See the Truth Table for a complete
description of read and write modes.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
1/12
1 page  
ESMT
www.DataSheet4U.com
M24L816512DA
Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14]
Parameter
Write Cycle[13]
tWC
tSCE
tAW
tHA
tSA
tPWE
Description
Write Cycle Time
CE1 LOW and CE2 HIGH to Write
End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
-55
Min.
55
45
45
0
0
40
tBW
BLE / BHE LOW to Write End
50
tSD Data Set-up to Write End
42
tHD Data Hold from Write End
0
tHZWE
WE LOW to High-Z[11, 12]
tLZWE
WE HIGH to Low-Z[11, 12]
5
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]
Max.
25
-70
Min. Max.
70
55
55
0
0
55
55
42
0
25
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle 2 ( OE Controlled)[14, 15]
Notes:
15. WE is HIGH for Read Cycle.
16. Device is continuously selected. OE , CE = VIL
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
5/12
5 Page 
ESMT
Revision History
Revision
1.0
1.1
www.DataSheet4U.com
M24L816512DA
Date
2007.07.04
2008.07.04
Description
Original
1. Move Revision History to the last
2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V
3. Add Industrial grade
4. Add Avoid timing
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M24L816512DA.PDF ] | |
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