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PDF M24L416256DA Data sheet ( Hoja de datos )
| Número de pieza | M24L416256DA | |
| Descripción | 4-Mbit (256K x 16) Pseudo Static RAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
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ESMT
PSRAM
www.DataSheet4U.com
M24L416256DA
4-Mbit (256K x 16) Pseudo Static RAM
Features
• Advanced low-power architecture
•High speed: 55 ns, 60 ns and 70 ns
•Wide voltage range: 2.7V to 3.6V
•Typical active current: 1 mA @ f = 1 MHz
•Low standby power
•Automatic power-down when deselected
Functional Description
The M24L416256DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 256K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode
reducing power consumption dramatically when deselected
( CE1 HIGH, CE2 LOW or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected ( CE1 HIGH, CE2
LOW, OE is HIGH), or during a write operation (Chip
Enabled and Write Enable WE LOW).
Reading from the device is accomplished by asserting the
Chip Enables ( CE1 LOW and CE2 HIGH) and Output
Enable( OE ) LOW while forcing the Write Enable ( WE ) HIGH.
If Byte Low Enable ( BLE ) is LOW, then data from the memory
location specified by the address pins A0 through A17 will
appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table for a complete description of read and write
modes.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
1/15
1 page  
ESMT
AC Test Loads and Waveforms
www.DataSheet4U.com
M24L416256DA
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics (Over the Operating Range)[10]
Prameter
Description
Read Cycle
tRC Read Cycle Time
tAA Address to Data Valid
tOHA Data Hold from Address Change
tACE CE1 LOW and CE2 HIGH to Data Valid
tDOE OE LOW to Data Valid
tLZOE
OE LOW to Low Z[11, 12]
tHZOE
OE HIGH to High Z[11, 12]
tLZCE
CE1 LOW and CE2 HIGH to Low Z[11,
12]
tHZCE
CE1 HIGH and CE2 LOW to High Z[11,
12]
tDBE BLE / BHE LOW to Data Valid
tLZBE
BLE / BHE LOW to Low Z[11, 12]
tHZBE
BLE / BHE HIGH to High-Z[11, 12]
tSK [14]
Address Skew
Write Cycle[13]
tWC Write Cycle Time
tSCE CE1 LOW and CE2 HIGH to Write End
tAW Address Set-up to Write End
tHA Address Hold from Write End
tSA Address Set-up to Write Start
–55
Min.
Max.
55[14]
5
5
5
55
55
25
25
25
55
5
10
0
55
45
45
0
0
–60
Min.
Max.
60
60
8
60
25
5
25
5
25
60
5
10
5
60
45
45
0
0
–70
Min.
Max.
70
70
10
70
35
5
25
5
25
70
5
25
10
70
60
55
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V
to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance.
11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of WE , CE1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input
set-up and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
5/15
5 Page 
ESMT
Truth Table[20]
www.DataSheet4U.com
M24L416256DA
CE1 CE2
HX
XL
XX
LH
LH
LH
LH
LH
LH
LH
LH
LH
WE
X
X
X
H
H
H
H
H
H
L
L
L
OE BHE BLE
Inputs/Outputs
Mode
Power
X X X High Z
Deselect/Power-down
Standby (ISB)
X X X High Z
Deselect/Power-down
Standby (ISB)
X H H High Z
Deselect/Power-down
Standby (ISB)
L L L Data Out (I/O0–I/O15) Read (Upper Byte and Lower Byte) Active (ICC)
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read (Upper Byte only)
Active (ICC)
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read (Lower Byte only)
Active (ICC)
H L L High Z
Output Disabled
Active (ICC)
H H L High Z
Output Disabled
Active (ICC)
H L H High Z
Output Disabled
Active (ICC)
X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC)
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High Z
Write (Lower Byte Only)
Active (ICC)
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write (Upper Byte Only)
Active (ICC)
Note:
20.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Ordering Information
Speed (ns)
55
60
70
55
60
70
55
60
70
55
60
70
Ordering Code
M24L416256DA-55BEG
M24L416256DA-60BEG
M24L416256DA-70BEG
M24L416256DA-55TEG
M24L416256DA-60TEG
M24L416256DA-70TEG
M24L416256DA-55BIG
M24L416256DA-60BIG
M24L416256DA-70BIG
M24L416256DA-55TIG
M24L416256DA-60TIG
M24L416256DA-70TIG
Package Type
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
44-pin TSOPII (Pb-Free)
Operating Range
Extended
Extended
Extended
Extended
Extended
Extended
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.5
11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M24L416256DA.PDF ] | |
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