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PDF 24AA1025 Data sheet ( Hoja de datos )

Número de pieza 24AA1025
Descripción 1024K I2C CMOS Serial EEPROM
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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24AA1025/24LC1025/24FC1025
1024K I2CSerial EEPROM
Device Selection Table:
Part
Number
VCC
Range
Max. Clock
Frequency
24AA1025 1.7-5.5V
400 kHz
24LC1025 2.5-5.5V 400 kHz*
24FC1025 1.8-5.5V
1 MHz
100 kHz for VCC < 2.5V
*100 kHz for VCC < 4.5V, E-temp
400 kHz for VCC < 2.5V
Temp.
Ranges
I
I, E
I
Features:
• Low-Power CMOS Technology:
- Read current 450 A, maximum
- Standby current 5 A, maximum
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIJ and SOIC
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description:
The Microchip Technology Inc. 24AA1025/24LC1025/
24FC1025 (24XX1025*) is a 128K x 8 (1024K bit)
Serial Electrically Erasable PROM, capable of
operation across a broad voltage range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
Package Type
PDIP
A0 1
A1 2
A2* 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SOIJ/SOIC
A0
A1
A2*
VSS
1
2
3
4
*A2 must be tied to VCC.
Block Diagram
8 VCC
7 WP
6 SCL
5 SDA
A0 A1 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
I/O SCL
SDA
VCC
VSS
EEPROM
Array
Page Latches
YDEC
Sense AMP
R/W Control
*24XX1025 is used in this document as a generic part number
for the 24AA1025/24LC1025/24FC1025 devices.
2005-2013 Microchip Technology Inc.
DS20001941L-page 1

1 page




24AA1025 pdf
24AA1025/24LC1025/24FC1025
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
A0
A1
A2
VSS
SDA
SCL
WP
VCC
PIN FUNCTION TABLE
PDIP
SOIJ
SOIC
1 11
2 22
3 33
4 44
5 55
6 66
7 77
8 88
Function
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard-wired to logical 1 state (VCC). Operation will
be undefined with this pin left floating or held to logical 0 (VSS).
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1025)
+2.5 to 5.5V (24LC1025)
+1.8 to 5.5V (24FC1025)
2.1 A0, A1 Chip Address Inputs
The A0 and A1 inputs are used by the 24XX1025 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2 A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to VCC in order for this device to operate.
If left floating or tied to VSS, device operation will be
undefined.
2.3 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 kfor 100 kHz, 2 kfor
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.4 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.5 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited, but read operations are
not affected.
2005-2013 Microchip Technology Inc.
DS20001941L-page 5

5 Page





24AA1025 arduino
24AA1025/24LC1025/24FC1025
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete. (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be resent. If the cycle is complete, then the device
will return the ACK and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
Note:
Care must be taken when polling the
24XX1025. The control byte that was
used to initiate the write needs to match
the control byte used for polling.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Yes
Next
Operation
No
2005-2013 Microchip Technology Inc.
DS20001941L-page 11

11 Page







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