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PDF P89V52X2 Data sheet ( Hoja de datos )
| Número de pieza | P89V52X2 | |
| Descripción | 8-bit 80C51 low power 8 kB fash microcontrolle | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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P89V52X2
8-bit 80C51 low power 8 kB flash microcontroller with 256 B
RAM, 192 B data EEPROM
Rev. 03 — 4 May 2009
Product data sheet
1. General description
The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and
192 B of data EEPROM. This device is designed to be a drop in and software compatible
replacement for the P87C52, P87C52X2, P89C52, and P89C52X2 devices.
2. Features
2.1 Principal features
I 0 MHz to 40 MHz operating frequency in 12× mode, 20 MHz in 6× mode
I 8 kB of on-chip flash user code memory
I 256 B of RAM
I Enhanced UART
I Three 16-bit timers/counters
I Four 8-bit I/O ports
I Supports 12-clock (default) or 6-clock mode selection via software or In-Circuit
Programming (ICP)
I DIP40, PLCC44, and LQFP44 packages
I Six interrupt sources with four priority levels
I Second DPTR register
2.2 Additional features
I Very low power
I Low EMI mode (ALE inhibit)
I Power-down mode with external interrupt wake-up
I Idle mode
I Extended temperature range
I Three security bits
I Programmable clock-out pin
1 page  
NXP Semiconductors
www.DataSheet4U.com
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
5.2 Pin description
Table 2. Pin description
Symbol
Pin
DIP40 LQFP44
P0[0] to P0[7]
P0[0]/AD0
39
P0[1]/AD1
38
P0[2]/AD2
37
P0[3]/AD3
36
P0[4]/AD4
35
P0[5]/AD5
34
P0[6]/AD6
33
P0[7]/AD7
32
P1[0] to P1[7]
37
36
35
34
33
32
31
30
P1[0]/T2
1
P1[1]/T2EX
2
P1[2]
P1[3]
P1[4]
P1[5]
P1[6]
3
4
5
6
7
40
41
42
43
44
1
2
PLCC44
43
42
41
40
39
38
37
36
2
3
4
5
6
7
8
Type Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O with
internal
pull-up
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have ‘1’s written to them float, and in this
state can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during
accesses to external code and data memory. In this
application, it uses strong internal pull-ups when
transitioning to ‘1’s. External pull-ups are required as a
general purpose I/O port.
P0[0] — Port 0 bit 0.
AD0 — Address/data bit 0.
P0[1] — Port 0 bit 1.
AD1 — Address/data bit 1.
P0[2] — Port 0 bit 2.
AD2 — Address/data bit 2.
P0[3] — Port 0 bit 3.
AD3 — Address/data bit 3.
P0[4] — Port 0 bit 4.
AD4 — Address/data bit 4.
P0[5] — Port 0 bit 5.
AD5 — Address/data bit 5.
P0[6] — Port 0 bit 6.
AD6 — Address/data bit 6.
P0[7] — Port 0 bit 7.
AD7 — Address/data bit 7.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. The Port 1 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 1 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups. P1[5], P1[6], P1[7] have high current
drive of 16 mA.
P1[0] — Port 1 bit 0.
T2 — External count input to Timer/Counter 2 or Clock-out
from Timer/Counter 2
P1[1] — Port 1 bit 1.
T2EX: Timer/Counter 2 capture/reload trigger and
direction control
P1[2] — Port 1 bit 2.
P1[3] — Port 1 bit 3.
P1[4] — Port 1 bit 4.
P1[5] — Port 1 bit 5.
P1[6] — Port 1 bit 6.
P89V52X2_3
Product data sheet
Rev. 03 — 4 May 2009
© NXP B.V. 2009. All rights reserved.
5 of 57
5 Page 
NXP Semiconductors
www.DataSheet4U.com
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.2 Memory organization
The various P89V52X2 memory spaces are as follows:
• DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect
addressing using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. This area includes the DATA area and the 128 B immediately
above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89V52X2 has 8 kB of on-chip Code memory.
6.3 System clock and clock options
6.3.1 Clock input options and recommended capacitor values for the oscillator
Shown in Figure 5 and Figure 6 are the input and output of an internal inverting amplifier
(XTAL1, XTAL2), which can be configured for use as an on-chip oscillator.
When driving the device from an external clock source, XTAL2 should be left disconnected
and XTAL1 should be driven. Power consumption can be further reduced by programming
the EXTCLK bit (UCFG.0).
At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to
interaction between the amplifier and its feedback capacitance. However, the capacitance
will not exceed 15 pF once the external signal meets the VIL and VIH specifications.
Resonator manufacturer, supply voltage, and other factors may cause circuit performance
to differ from one application to another. C1 and C2 should be adjusted appropriately for
each design. Table 4 shows the typical values for C1 and C2 vs. resonator type for various
frequencies.
Table 4. Recommended values for C1 and C2 by crystal type
Resonator
C1 = C2
Quartz
20 pF to 30 pF
Ceramic
40 pF to 50 pF
P89V52X2_3
Product data sheet
Rev. 03 — 4 May 2009
© NXP B.V. 2009. All rights reserved.
11 of 57
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