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PDF P89LPC980 Data sheet ( Hoja de datos )

Número de pieza P89LPC980
Descripción 8-bit microcontroller
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! P89LPC980 Hoja de datos, Descripción, Manual

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P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core,
4 kB/8 kB wide-voltage byte-erasable flash with 10-bit ADC
Rev. 02 — 8 February 2010
Preliminary data sheet
1. General description
The P89LPC980/982/983/985 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes instructions
in two to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC980/982/983/985 in order to reduce
component count, board space, and system cost.
2. Features
2.1 Principal features
„ 4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
„ 256-byte RAM data memory. Both the P89LPC982 and the P89LPC985 also include a
256-byte auxiliary on-chip RAM.
„ 8-input multiplexed 10-bit ADC (P89LPC985, 4-input multiplexed 10-bit ADC on
P89LPC983) with window comparator that can generate an interrupt for in or out of
range results. Two analog comparators with selectable inputs and reference source.
„ Five 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
„ A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
„ Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
„ High-accuracy internal RC oscillator option 7.373 MHz calibrated to ±1 %, with clock
doubler option, allows operation without external oscillator components. The RC
oscillator option is selectable and fine tunable.
„ Watchdog timer with separate on-chip oscillator, nominal 400 kHz/25 kHz, calibrated to
±10 % at 400 kHz, requiring no external components. The watchdog prescaler is
selectable from eight values.
„ Pin remap for UART, I2C and SPI.
„ 2.4 V to 5.5 V VDD operating range.
„ Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
„ 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins
while using on-chip oscillator and reset options.

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P89LPC980 pdf
NXP Semiconductors
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P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC983/985
ACCELERATED 2-CLOCK 80C51 CPU
P3[1:0]
P2[7:0]
P1[7:0]
P0[7:0]
CRYSTAL
OR
RESONATOR
XTAL1
XTAL2
8 kB/4 kB
CODE FLASH
256-BYTE
DATA RAM
internal bus
256-BYTE
AUXILIARY RAM
(P89LPC985)
PORT 3
CONFIGURABLE I/Os
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
clock
CONFIGURABLE
OSCILLATOR
ON-CHIP RC
OSCILLATOR
WITH CLOCK
DOUBLER
(1) Only on the P89LPC985.
Fig 2. P89LPC983/985 block diagram
UART
I2C-BUS
SPI
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
TIMER 2
TIMER 3
TIMER 4
ANALOG
COMPARATORS
10-BIT ADC
POWER MANAGEMENT
(POWER-ON RESET,
BROWNOUT RESET,
REGULATORS)
002aae533
TXD
RXD
SCL
SDA
SPICLK
MOSI
MISO
SS
T0
T1
T2
T2EX
T3
T3EX
T4
T4EX
CMP2
CIN2B
CIN2A
CMP1
CIN1A
CIN1B
AD00
AD01
AD02
AD03
AD04(1)
AD05(1)
AD06(1)
AD07(1)
P89LPC980_982_983_985_2
Preliminary data sheet
Rev. 02 — 8 February 2010
© NXP B.V. 2010. All rights reserved.
5 of 85

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P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
Table 3. Pin description …continued
Symbol
Pin Type Description
PLCC28,
TSSOP28
P0.6/CMP1/KBI6 20
I/O P0.6 — Port 0 bit 6. High current source.
O CMP1 — Comparator 1 output.
I KBI6 — Keyboard input 6.
P0.7/KBI7/T1
19
I/O P0.7 — Port 0 bit 7. High current source.
I/O T1 — Timer/counter 1 external count input or overflow output.
I KBI7 — Keyboard input 7.
P1.0 to P1.7
I/O, I
[1]
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for
three pins as noted below. During reset Port 1 latches are configured in the input
only mode with the internal pull-up disabled. The operation of the configurable
Port 1 pins as inputs and outputs depends upon the port configuration selected.
Each of the configurable port pins are programmed independently. Refer to Section
7.16.1 “Port configurations” and Table 13 “Static characteristics” for details. P1.2 to
P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt trigger inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 18 I/O P1.0 — Port 1 bit 0.
O TXD — Transmitter output for serial port.
P1.1/RXD/T2EX 17
I/O P1.1 — Port 1 bit 1.
I RXD — Receiver input for serial port.
I T2EX — Timer/counter 2 external capture input.
P1.2/SCL/T0
12
I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when
used as output).
I/O SCL — I2C-bus serial clock input/output.
P1.3/INT0/SDA/ 11
T4
I/O P1.3 — Port 1 bit 3 (open-drain when used as output).
I INT0 — External interrupt 0 input.
I/O SDA — I2C-bus serial data input/output.
I/O T4 — Timer/counter 4 external count input or overflow output.
P1.4/INT1/T4EX/ 10
SS
I/O P1.4 — Port 1 bit 4. High current source.
I INT1 — External interrupt 1 input.
I T4EX — Timer/counter 4 external capture input.
I SS — SPI Slave select. (pin remap)
P1.5/RST
6
I P1.5 — Port 1 bit 5 (input only).
I RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
P1.6/MISO
5
I/O P1.6 — Port 1 bit 6. High current source.
I/O MISO — SPI master in slave out.When configured as master, this pin is input,
when configured as slave, this pin is output. (pin remap)
P89LPC980_982_983_985_2
Preliminary data sheet
Rev. 02 — 8 February 2010
© NXP B.V. 2010. All rights reserved.
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