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PDF LH7A400 Data sheet ( Hoja de datos )
| Número de pieza | LH7A400 | |
| Descripción | 32-Bit System-on-Chip | |
| Fabricantes | SHARP Electronic | |
| Logotipo |  |
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Preliminary Data Sheet
www.DataSheet4U.com
LH7A400
32-Bit System-on-Chip
FEATURES
• ARM922T™ Core:
– 32-bit ARM9TDMI™ RISC Core
– 16KB Cache: 8KB Instruction Cache and
8KB Data Cache
– MMU (Windows CE Enabled)
• High Performance (200 MHz)
• 80KB On-Chip Memory
• External Bus Interface
– 100 MHz
– Asynchronous SRAM/ROM/Flash
– Synchronous DRAM/Flash
– PCMCIA
– CompactFlash
• Clock and Power Management
– 32.768 kHz and 14.7456 MHz Oscillators
– Programmable PLL
• Low Power Modes
– Run (147 mA), Halt (41 mA), Standby (42 µA)
• Programmable LCD Controller
– Up to 1,024 × 768 Resolution
– Supports STN, Color STN, AD-TFT, HR-TFT, TFT
– Up to 64,000 Colors and 15 Gray Shades
• DMA (10 Channels)
– AC97
– MMC
– USB
• USB Device Interface (USB 1.1)
• Synchronous Serial Port (SSP)
– Motorola SPI™
– Texas Instruments SSI
– National MICROWIRE™
• Three Programmable Timers
• Three UARTs
– Classic IrDA (115 kbit/s)
• Smart Card Interface (ISO7816)
• DC-to-DC Converters
• MultiMediaCard™ Interface
• AC97 Codec Interface
• Smart Battery Monitor Interface
• Real Time Clock (RTC)
• Up to 60 General Purpose I/Os
• Programmable Interrupt Controller
• Watchdog Timer
• JTAG Debug Interface and Boundary Scan
• Operating Voltage
– 1.8 V Core
– 3.3 V Input/Output (1.8 V I/O Optional1)
• 5 V Tolerant Inputs (except oscillator pins2)
• Operating Temperature
– 0°C to +70°C Commercial
– -40°C to +85°C Industrial (With Clock Frequency
Reduction1)
• 256-Ball PBGA or 256-Ball CABGA Package
DESCRIPTION
The LH7A400, powered by an ARM922T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
This high degree of integration lowers overall sys-
tem costs, reduces development cycle time and accel-
erates product introduction.
Motorola SPI is a trademark of Motorola, Inc.
National Semiconductor MICROWIRE is a trademark of
National Semiconductor Corporation.
Windows CE is a trademark of Microsoft Corporation.
Preliminary Data Sheet
NOTES:
1. Under development. Results pending further characterization.
2. Oscillator pins R13, T13, P15, and P16 are 1.8 V ±10%
12/8/03
1
1 page  
32-Bit System-on-Chip
PBGA CABGA
PIN PIN
SIGNAL
L12 L11 D0
M15 L13 D1
N13 L14 D2
L16 K11 D3
L15 L16 D4
L14 K14 D5
H11 J15 D6
K12 J12 D7
J15 J10 D8
J13 H16 D9
J10 H14 D10
H15 H11 D11
H13 G16 D12
G15 G9 D13
G11 G14 D14
G12 G12 D15
F15 F15 D16
F12 E15 D17
E14 D16 D18
D16 F12 D19
H10 E13 D20
D14 D14 D21
F10 E12 D22
A16 B16 D23
A14 D12 D24
B13 A16 D25
C13 B13 D26
E12 B14 D27
G10 C12 D28
B12 A14 D29
B11 B12 D30
D11 A12 D31
M16 M15 A0/nWE1
N14 M16 A1/nWE2
Table 1. Functional Pin List (Cont’d)
DESCRIPTION
RESET
STATE
LH7A400
www.DataSheet4U.com
STANDBY OUTPUT
STATE
DRIVE
Data Bus
LOW
LOW
12 mA
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 1
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 2
HIGH: nWE1 HIGH
HIGH: nWE2 HIGH
12 mA
12 mA
Preliminary Data Sheet
12/8/03
5
5 Page 
32-Bit System-on-Chip
LH7A400
www.DataSheet4U.com
PBGA CABGA
PIN PIN
SIGNAL
J7 G3 UARTRX2
H4 J3 SSPCLK
J1 J6 SSPRX
J2 J7 SSPTX
J3
J2
SSPFRM/
nSSPFRM
F6 G2 COL0
F5 G1 COL1
G1 H3 COL2
G2 H5 COL3
G4 H6 COL4
G5 H7 COL5
H1 H2 COL6
H2 H1 COL7
H3 J1 TBUZ
C3 F5 MEDCHG
P11 T14 WIDTH0
R12 T15 WIDTH1
D1 E3 BATOK
D2 F6 nBATCHG
A1 E5 TDI
B1 C2 TCK
B2 D3 TDO
C1 C1 TMS
T12 P15 nTEST0
R15 P13 nTEST1
Table 1. Functional Pin List (Cont’d)
DESCRIPTION
RESET
STATE
UART2 Receive Data Input. This pin is an output
for JTAG boundary scan only.
Input
Synchronous Serial Port Clock
LOW
Synchronous Serial Port Receive
Input
Synchronous Serial Port Transmit
LOW
Synchronous Serial Port Frame Sync
Input:
nSSPFRM
STANDBY OUTPUT
STATE
DRIVE
Input
LOW
Input
LOW
Input
8 mA
8 mA
8 mA
Keyboard Interface
HIGH
HIGH
8 mA
Timer Buzzer (254 kHz MAX.)
LOW
LOW
Boot Device Media Change. Used with the
WIDTH0 and WIDTH1 pins to specify boot mem- Input (Schmitt) Input
ory device.
External Memory Width Pins. Also, used with
MEDCHG to specify the boot memory device size.
Input (Schmitt)
Input
Battery OK
Input (Schmitt) Input
Battery Change
Input (Schmitt) Input
JTAG Data In. This signal is internally pulled-up Input with
to VDD.
Pull-up
Input with
Pull-up
JTAG Clock. This signal should be externally
pulled-up to VDD.
Input
Input
JTAG Data Out. This signal should be externally
pulled up to VDD with a 33 kΩ resistor.
Input
No Change
JTAG Test Mode select. This signal is internally Input with
pulled-up to VDD.
Pull-up
Input with
Pull-up
Test Pin 0. Internally pulled up to VDD. For Normal
mode, leave open. For JTAG mode, tie to GND.
See Table 2.
Input with
Pull-up
Input with
Pull-up
Test Pin 1. internally pulled up to VDD. For Normal Input with
and JTAG mode, leave open. See Table 2.
Pull-up
Input with
Pull-up
8 mA
4 mA
NOTES: *Signals beginning with ‘n’ are Active LOW.
Table 2. nTest Pin Function
MODE
JTAG
Normal
nTEST0
0
1
nTEST1
1
1
nURESET
1
x
Preliminary Data Sheet
12/8/03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LH7A400.PDF ] | |
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