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PDF LH7A400 Data sheet ( Hoja de datos )
| Número de pieza | LH7A400 | |
| Descripción | 32-Bit System-on-Chip | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Preliminary data sheet
www.DataSheet4U.com
LH7A400
32-Bit System-on-Chip
FEATURES
• 32-bit ARM9TDMI™ RISC Core
– 16 kB Cache: 8 kB Instruction and 8 kB Data
– MMU (Windows CE™ Enabled)
– Up to 250 MHz; see Table 1 for options
• 80 kB On-Chip Static RAM
• Programmable Interrupt Controller
• External Bus Interface
– Up to 125 MHz; see Table 1 for options
– Asynchronous SRAM/ROM/Flash
– Synchronous DRAM/Flash
– PCMCIA
– CompactFlash
• Clock and Power Management
– 32.768 kHz and 14.7456 MHz Oscillators
– Programmable PLL
• Programmable LCD Controller
– Up to 1,024 × 768 Resolution
– Supports STN, Color STN, AD-TFT, HR-TFT, TFT
– Up to 64 k-Colors and 15 Gray Shades
• DMA (10 Channels)
– AC97
– MMC
– USB
• USB Device Interface (USB 2.0, Full Speed)
• Synchronous Serial Port (SSP)
– Motorola SPI™
– Texas Instruments SSI
– National MICROWIRE™
• Three Programmable Timers
• Three UARTs
– Classic IrDA (115 kbit/s)
• Smart Card Interface (ISO7816)
• Two DC-to-DC Converters
• MultiMediaCard™ Interface
• AC97 Codec Interface
• Smart Battery Monitor Interface
• Real Time Clock (RTC)
• Up to 60 General Purpose I/Os
• Watchdog Timer
• JTAG Debug Interface and Boundary Scan
• Operating Voltage
– 1.8 V Core
– 3.3 V Input/Output
• 5 V Tolerant Digital Inputs (except oscillator pins)
– Oscillator pins P15, P16, R13, and T13 are
1.8 V ± 10 %.
• Operating Temperature: −40°C to +85°C
• 256-ball BGA or 256-ball LFBGA Package
DESCRIPTION
The LH7A400, powered by an ARM922T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
This high degree of integration lowers overall
system costs, reduces development cycle time and
accelerates product introduction.
PART NUMBER
LH7A400N0F076B5
LH7A400N0F000B3A
LH7A400N0F000B5
LH7A400N0G000B5
CORE
CLOCK
250 MHz/
245 MHz
200 MHz/
195 MHz
200 MHz/
195 MHz
200 MHz/
195 MHz
Table 1. LH7A400 versions
BUS
CLOCK
LOW POWER CURRENT BY MODE (TYP.)
125 MHz Run = 250 mA; Halt = 50 mA; Standby = 129 µA
100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA
100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA
100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA
TEMP. RANGE
0°C to +70°C/
−40°C to +85°C
0°C to +70°C/
−40°C to +85°C
0°C to +70°C/
−40°C to +85°C
0°C to +70°C/
−40°C to +85°C
Preliminary data sheet
1
1 page  
32-Bit System-on-Chip
BGA
PIN
G7
F1
K7
M1
M5
T6
R14
M14
J11
J12
F13
B14
E10
B8
H7
G3
K4
N5
P6
T14
R16
N16
K13
H9
C15
A11
E8
A5
F7
E1
J4
P3
T8
K9
L13
E15
D12
A7
H5
M3
L9
T10
N15
H12
B15
C9
G6
LFBGA
PIN
SIGNAL
C10
F9
F11
F14
G8
H13
J9
VDD
K15
L7
N6
N8
N12
N13
P11
B8
C6
D5
D13
E8
F7
G13
H9 VSS
J14
K7
L8
L10
L12
M11
M14
C4
D7
D10
F4
F10 VDDC
J4
J8
K8
L6
G7
H4
H8
L4
L9 VSSC
N3
N7
N10
R5
NXP Semiconductors
Table 3. Functional Pin List
DESCRIPTION
RESET
STATE
I/O Ring Power
I/O Ring Ground
Core Power
Core Ground
LH7A400
www.DataSheet4U.com
STANDBY
STATE
OUTPUT
DRIVE
I/O
NOTES
Preliminary data sheet
Rev. 01 — 16 July 2007
5
5 Page 
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
www.DataSheet4U.com
Table 3. Functional Pin List (Cont’d)
BGA
PIN
P9
N9
P7
R7
T7
N8
T15
T16
E7
D7
C7
B7
C4
D5
B4
A4
A3
B3
A2
E2
E3
E5
F2
F3
F4
J7
H4
J1
J2
J3
LFBGA
PIN
SIGNAL
P9
LCDENAB/
LCDM
N9 LCDDCLK
M8 LCDVD0
P8 LCDVD1
R8 LCDVD2
T8 LCDVD3
T16 USBDP
R16 USBDN
C7 nPWME0
A6 nPWME1
B6 PWM0
B5 PWM1
A2 ACBITCLK
A1 ACOUT
B2 ACSYNC
E6 ACIN
C3
MMCCLK/
MMSPICLK
B1
MMCCMD/
MMSPIDIN
D4
MMCDATA/
MMSPIDOUT
E1 UARTCTS2
F3 UARTDCD2
G4 UARTDSR2
G5 UARTIRTX1
G6 UARTIRRX1
F1 UARTTX2
G3 UARTRX2
J3 SSPCLK
J6 SSPRX
J7 SSPTX
J2
SSPFRM/
nSSPFRM
DESCRIPTION
LCD TFT Data Enable
LCD STN AC Bias
LCD Data Clock
RESET
STATE
LOW:
LCDENAB
LOW
LCD Video Data Bus
LOW
USB Data Positive (Differential Pair)
Input
USB Data Negative (Differential Pair)
Input
• DC-DC Converter Pulse Width
• Modulator 0 Enable
Input
• DC-DC Converter Pulse Width
• Modulator 1 Enable
Input
• DC-DC Converter Pulse Width
• Modulator 0 Output during normal operation and
Polarity Selection input at reset
Input
• DC-DC Converter Pulse Width
• Modulator 1 Output during normal operation and
Polarity Selection input at reset
Input
• Audio Codec (AC97) Clock
• Audio Codec (ACI) Clock
Input
• Audio Codec (AC97) Output
• Audio Codec (ACI) Output
LOW
• Audio Codec (AC97)
Synchronization
• Audio Codec (ACI) Synchronization
LOW
• Audio Codec (AC97) Input
• Audio Codec (ACI) Input
Input
• MultiMediaCard Clock (20 MHz MAX.)
• MultiMediaCard SPI Mode Clock
LOW:
MMCCLK
• MultiMediaCard Command
• MultiMediaCard SPI Mode Data Input
Input:
MMCCMD
• MultiMediaCard Data
• MultiMediaCard SPI Mode Data Output
Input:
MMCDATA
• UART2 Clear to Send Signal. This pin is an
output for JTAG boundary scan only.
Input
• UART2 Data Carrier Detect Signal. This pin is
output for JTAG boundary scan only.
Input
UART2 Data Set Ready Signal
Input
IrDA Transmit
LOW
IrDA Receive. This pin is an output for JTAG
boundary scan only.
Input
UART2 Transmit Data Output
HIGH
UART2 Receive Data Input. This pin is an output
for JTAG boundary scan only.
Input
Synchronous Serial Port Clock
LOW
Synchronous Serial Port Receive
Input
Synchronous Serial Port Transmit
LOW
Synchronous Serial Port Frame Sync
Input
STANDBY
STATE
LOW
LOW
LOW
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
LOW
Input
Input
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
LOW
Input
OUTPUT
DRIVE
I/O
NOTES
12 mA O
12 mA
12 mA
O
O
O
O
O
I/O
I/O
I
10
10
I
8 mA I/O
8 mA I/O
8 mA I/O
8 mA O
8 mA O
I
8 mA O
8 mA I/O
8 mA I/O
I
8 mA
8 mA
8 mA
8 mA
8 mA
I
I
O
I
O
I
O
I
I/O
I/O
Preliminary data sheet
Rev. 01 — 16 July 2007
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LH7A400.PDF ] | |
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