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Número de pieza KSZ8873FLL
Descripción Integrated 3-Port 10/100 Managed Switch
Fabricantes Micrel Semiconductor　
Logotipo Micrel Semiconductor Logotipo



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No Preview Available ! KSZ8873FLL Hoja de datos, Descripción, Manual

KSZ8873MLL/FLL/RLL
Integrated 3-Port 10/100 Managed Switch
with PHYs
Revision 1.6
General Description
The KSZ8873MLL/FLL/RLL are highly-integrated 3-port
switches on a chip ICs in the industry’s smallest footprint.
They are designed to enable a new generation of low port
count, cost-sensitive, and power-efficient 10/100Mbps
switch systems. Low power consumption, advanced power
management and sophisticated QoS features (e.g., IPv6
priority classification support) make these devices ideal for
IPTV, IP-STB, VoIP, automotive, and industrial
applications.
The KSZ8873 family is designed to support the GREEN
requirement in today’s switch systems. Advanced power
management schemes include hardware power down,
software power down, per port power down and the energy
detect mode that shuts downs the transceiver when a port
is idle.
KSZ8873MLL/FLL/RLL also offers a by-pass mode. In this
mode, the processor connected to the switch through the
MII interface can be shut down without impacting the
normal switch operation.
The configurations provided by the KSZ8873 family
enables the flexibility to meet requirements of different
applications:
• KSZ8873MLL: Two 10/100BASE-T/TX transceivers
and one MII interface.
• KSZ8873RLL: Two 10/100BASE-T/TX transceivers
and one RMII interface.
• KSZ8873FLL: Two 100BASE-FX transceivers and one
MII interface.
The device is available in RoHS-compliant 64-pin LQFP
package. Industrial-grade and qualified AEC-Q100
Automotive-grade version are also available (see Ordering
Information section)
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 20, 2013
Revision 1.6

1 page




KSZ8873FLL pdf
Micrel, Inc.
KSZ8873MLL/FLL/RLL
Advanced Switch Functions .................................................................................................................................................. 36
Bypass Mode ..................................................................................................................................................................... 36
IEEE 802.1Q VLAN Support.............................................................................................................................................. 36
QoS Priority Support.......................................................................................................................................................... 37
Port-Based Priority ............................................................................................................................................................ 37
802.1p-Based Priority ........................................................................................................................................................ 37
DiffServ-Based Priority................................................................................................................................................... 38
Spanning Tree Support ..................................................................................................................................................... 38
Rapid Spanning Tree Support ........................................................................................................................................... 39
Tail Tagging Mode ............................................................................................................................................................. 39
IGMP Support .................................................................................................................................................................... 40
IGMP Snooping.............................................................................................................................................................. 40
IGMP Send-Back to the Subscribed Port ...................................................................................................................... 40
Port Mirroring Support ....................................................................................................................................................... 40
Rate Limiting Support ........................................................................................................................................................ 41
Unicast MAC Address Filtering.......................................................................................................................................... 41
Configuration Interface ...................................................................................................................................................... 41
I2C Master Serial Bus Configuration .............................................................................................................................. 41
I2C Slave Serial Bus Configuration ................................................................................................................................ 42
SPI Slave Serial Bus Configuration ............................................................................................................................... 43
Loopback Support ............................................................................................................................................................. 46
Far-End Loopback ......................................................................................................................................................... 46
Near-End (Remote) Loopback ....................................................................................................................................... 47
MII Management (MIIM) Registers........................................................................................................................................ 48
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control................................................................................ 49
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control................................................................................ 49
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status ................................................................................. 50
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status ................................................................................. 50
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High........................................................................................ 50
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High........................................................................................ 50
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low ........................................................................................ 50
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low ........................................................................................ 50
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability ............................................. 51
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability ............................................. 51
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability ................................................. 51
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability ................................................. 51
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): Not supported................................................................................ 52
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status .................................................................. 52
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status........................................................... 52
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status........................................................... 52
Memory Map (8-Bit Registers) .............................................................................................................................................. 53
Global Registers ................................................................................................................................................................ 53
Port Registers .................................................................................................................................................................... 53
Advanced Control Registers.............................................................................................................................................. 53
September 20, 2013
5
Revision 1.6

5 Page





KSZ8873FLL arduino
Micrel, Inc.
KSZ8873MLL/FLL/RLL
List of Tables
Table 1. FX Signal Threshold................................................................................................................................................ 20
Table 2. MDI/MDI-X Pin Definitions ...................................................................................................................................... 21
Table 3. Internal Function Block Status ................................................................................................................................ 25
Table 4. MII Signals .............................................................................................................................................................. 32
Table 5. RMII Clock Setting .................................................................................................................................................. 33
Table 6. RMII Signal Description........................................................................................................................................... 33
Table 7. RMII Signal Connections......................................................................................................................................... 34
Table 8. MII Management Interface Frame Format .............................................................................................................. 35
Table 9. Serial Management Interface (SMI) Frame Format ................................................................................................ 35
Table 10. FID + DA Lookup in VLAN Mode .......................................................................................................................... 36
Table 11. FID + SA Lookup in VLAN Mode .......................................................................................................................... 36
Table 12. Spanning Tree States ........................................................................................................................................... 38
Table 13. Tail Tag Rules ....................................................................................................................................................... 40
Table 14. SPI Connections ................................................................................................................................................... 44
Table 15. Data Rate Limit Table ........................................................................................................................................... 67
Table 16. Format of Static MAC Table (8 Entries) ................................................................................................................ 91
Table 17. Format of Static VLAN Table (16 Entries)............................................................................................................. 93
Table 18. Format of Dynamic MAC Address Table (1K Entries) .......................................................................................... 94
Table 19. Format of “Per Port” MIB Counters ....................................................................................................................... 95
Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets................................................................................... 96
Table 21. Format of “All Port Dropped Packet” MIB Counters.............................................................................................. 97
Table 22. “All Port Dropped Packet” MIB Counters .............................................................................................................. 97
Table 23. EEPROM Timing Parameters ............................................................................................................................. 101
Table 24. MAC Mode MII Timing Parameters..................................................................................................................... 102
Table 25. PHY Mode MII Timing Parameters ..................................................................................................................... 103
Table 26. RMII Timing Parameters ..................................................................................................................................... 104
Table 27. I2C Timing Parameters........................................................................................................................................ 106
Table 28. SPI Input Timing Parameters.............................................................................................................................. 107
Table 29. SPI Output Timing Parameters ........................................................................................................................... 108
Table 30. Auto-Negotiation Timing Parameters.................................................................................................................. 109
Table 31. MDC/MDIO Timing Parameters .......................................................................................................................... 110
Table 32. Reset Timing Parameters ................................................................................................................................... 111
Table 33. Transformer Selection Criteria ............................................................................................................................ 113
Table 34. Qualified Single-Port Magnetics.......................................................................................................................... 113
Table 35. Typical Reference Crystal Characteristics .......................................................................................................... 113
September 20, 2013
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Revision 1.6

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