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PDF L6747C Data sheet ( Hoja de datos )
| Número de pieza | L6747C | |
| Descripción | High Current MOSFET Driver | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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L6747C
High current MOSFET driver
Features
■ Dual MOSFET driver for synchronous rectified
converters
■ High driving current for fast external MOSFET
switching
■ High frequency operation
■ Enable pin
■ Adaptive dead-time management
■ Flexible gate-drive: 5 V to 12 V compatible
■ High-impedance (HiZ) management for output
stage shutdown
■ Preliminary overvoltage (OV) protection
■ VFDFPN8 3x3 mm package
Applications
■ High current VRM / VRD for desktop / server /
workstation CPUs
■ High current and high efficiency DC-DC
converters
Description
The L6747C is a flexible, high-frequency dual-
driver specifically designed to drive N-channel
MOSFETs connected in synchronous-rectified
buck topology.
Combined with ST PWM controllers, the driver
allows the implementation of complete voltage
VFDFPN8 3x3 mm
regulator solutions for modern high-current CPUs
and for DC-DC conversion in general.
The L6747C embeds high-current drivers for both
high-side and low-side MOSFETS. The device
accepts a flexible power supply of 5 V to 12 V.
This allows optimization of the high-side and low-
side gate-drive voltage to maximize system
efficiency.
Anti shoot-through management prevents the
high-side and low-side MOSFETs from
conducting simultaneously and, combined with
adaptive dead-time control, minimizes the LS
body diode conduction time.
The L6747C features preliminary OV protection to
protect the load from dangerous overvoltage due
to MOSFET failures at startup.
The driver is available in a VFDFPN8 3x3 mm
package.
Table 1.
Device summary
Order codes
L6747C
L6747CTR
Package
VFDFPN8
VFDFPN8
Packing
Tube
Tape and reel
April 2010
Doc ID 17127 Rev 1
1/15
www.st.com
15
1 page  
L6747C
www.DataSheet4U.com
Pin information and thermal data
Table 2. Pin descriptions (continued)
Pin # Name
Function
High-side driver output.
8 UGATE Connect to high-side MOSFET gate. A small series resistor may be used to
control the PHASE pin negative spike.
-
TH. PAD
Thermal pad connects the silicon substrate and makes good thermal contact
with the PCB. Connect to the PGND plane.
2.2
Thermal data
Table 3. Thermal data
Symbol
Parameter
RTHJA
RTHJC
TMAX
TSTG
TJ
PTOT
Thermal resistance junction-to-ambient
(device soldered on 2s2p, 67mm x 69mm board)
Thermal resistance junction-to-case
Maximum junction temperature
Storage temperature range
Junction temperature range
Maximum power dissipation at 25°C
(device soldered on 2s2p,67mm x 69mm board)
Value
Unit
45 °C/W
5
150
0 to 150
0 to 125
°C/W
°C
°C
°C
2.25 W
Doc ID 17127 Rev 1
5/15
5 Page 
L6747C
www.DataSheet4U.com
Device description and operation
MOSFET to reach the driving voltage (PVCC for HS and VCC for LS). This capacitor is
charged and discharged at the driver switching frequency FSW.
The total power PSW is dissipated among the resistive components distributed along the
driving path. According to the external gate resistance and the power MOSFET intrinsic
gate resistance, the driver dissipates only a portion of PSW as follows:
PSW – HS
=
1--
2
⋅
CGHS
⋅
PVCC2
⋅
Fsw
⋅
⎛
⎝
-------------------------R----h---i--H---S--------------------------
RhiHS + RGateHS + RiHS
+
-R----l-o---H----S-----+-----R--R--G--l--oa---Ht--e-S--H---S-----+-----R-----i-H----S-⎠⎞
PSW – LS
=
1--
2
⋅
CGLS
⋅
VCC2
⋅
Fsw
⋅
⎛
⎝
------------------------R-----h---i-L---S-------------------------
RhiLS + RGateLS + RiLS
+
-R----l-o---L---S-----+-----R--R--G---l-oa---Lt--e-S--L---S-----+----R-----i-L---S--⎠⎞
The total power dissipated from the driver can then be determined as follows:
P = PDC + PSW – HS + PSW – LS
Figure 6. Equivalent circuit for a MOSFET driver
VCC
VCC
BOOT
RGATELS RILS
LGATE
CGLS
GND
LS DRIVER
LS MOSFET
RGATEHS RIHS
HGATE
CGHS
PHASE
HS DRIVER
HS MOSFET
4.5 Layout guidelines
L6747C provides driving capability to implement high-current step-down DC-DC converters.
The first priority when placing components for these applications should be given to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (as well as EMI and losses) power connections must be
part of a power plane, and in any case constructed with wide and thick copper traces. The
loop must be minimized. The critical components, such as the power MOSFETs, must be
close to each other. However, some space between the power MOSFETs is required to
assure good thermal cooling and airflow.
Traces between the driver and the MOSFETS should be short and wide to minimize the
inductance of the trace, which in turn minimizes ringing in the driving signals. Moreover, the
VIA count should be minimized to reduce the related parasitic effect.
The use of a multi-layer printed circuit board is recommended.
Small signal components and connections to critical nodes of the application, as well as
bypass capacitors for the device supply, are also important. Place the bypass capacitor
Doc ID 17127 Rev 1
11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet L6747C.PDF ] | |
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