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PDF L6717 Data sheet ( Hoja de datos )
| Número de pieza | L6717 | |
| Descripción | High-efficiency hybrid AM2r2 controller | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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L6717
High-efficiency hybrid AM2r2 controller
with I2C interface and embedded drivers
Features
■ Hybrid controller for both PVI and SVI CPUs
■ Dual controller with 2 embedded high current
drivers + 2 PWM for external driver for CPU
CORE and 1 embedded high current driver for
CPU NB
■ Dynamic phase management (DPM)
■ I2C interface to control offset, switching
frequency and power management options
■ Dual-edge asynchronous architecture with LTB
technology®
■ PSI management to increase efficiency in light-
load conditions
■ Dual overcurrent protection: Total and per-
phase
■ Accurate voltage positioning
■ Dual remote sense
■ Feedback disconnection protection
■ Programmable OV protection
■ Oscillator internally fixed at 200 kHz externally
adjustable
■ LSLess startup to manage pre-biased output
■ VFQFPN48 Package
Applications
■ Hybrid high-current VRM / VRD for desktop /
Server / Workstation / IPC CPUs supporting
PVI and SVI interface
■ High-density DC / DC converters
VFQFPN48
VFQFPN48
Description
L6717 is a hybrid CPU power supply controller
embedding 2 high-current drivers for the CORE
section and 1 driver for the NB section - requiring
up to 2 external drivers when the CORE section
works at 4 phase to optimize the application over-
all cost.
I2C interface allows to manage offset both CORE
and NB sections, switching frequency and
dynamic phase management saving in
component count, space and power consumption.
Dynamic phase management automatically
adjusts phase-count according to CPU load
optimizing the system efficiency under all load
conditions.
Tophteimdiuzaeld-ebdygLeTaBsytencchhnroonlooguys®aarcllhoiwteinctgurfaesitsload-
transient response minimizing the output
capacitor and reducing the total BOM cost.
Fast protection against load over current is
provided for both the sections. Feedback
disconnection protection prevents from damaging
the load in case of disconnections in the system
board.
Table 1. Device summary
L6717 is available in VFQFPN48 package.
Order codes
Package
Packing
L6717
L6717TR
VFQFPN48
Tray
Tape and reel
March 2010
Doc ID 17326 Rev 1
1/56
www.st.com
56
1 page  
L6717
Figure 2. Typical 3+1 application circuit
CHF
CHF
3 2 49 42
48
BOOT1
PVI / SVID Bus
5V SBY
R OSC
PWRGOOD
35
PWROK
1
VID0 / VFIX
34
VID1 / CORE_TYPE
33
VID2 / SVD
32
VID3 / SVC
31
VID4 / I2C_DIS
30
VID5 / ADDRESS
29
OSC / EN / FLT
14
Q_EN
EN
R ILIM
ILIM
13
C ILIM
UGATE1
PHASE1
LGATE1
47
46
45
HS1
LS1
CS1P
CS1N
CS3N
CS3P
PWM3
BOOT2
15
16
20
19
28
39
UGATE2
PHASE2
LGATE2
40
41
44
RG
RG
HS2
LS2
SCL / OS
Power Manager I2C 26
SDA / OVP
25
CS2P
CS2N
CS4N
CS4P
PWM4
17
18
22
21
27
RG
RG
COMP
4
CF
C
RF
FB
5
CI
RFB
RI
LTB
8
CLTB
RLTB
VSEN
6
FBG
7
36
NB_BOOT
NB_UGATE
NB_PHASE
NB_LGATE
37
38
43
HS_NB
LS_NB
23
NB_CSP
NB_CSN
24 RG_NB
12
NB_FBG
9 10 11
CF_NB RF_NB
RFB_NB
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Typical application circuit and block diagram
LIN
CBULK_IN
VIN
CHF
L1
R
C
CHF
HS3
L3
R
C
LS3
VCC
BOOT
3.3V
UGATE
PHASE
LGATE
GND
EN
PWM
CHF
L2
R
C
CHF
L_NB
R_NB
C_NB
COUT_NB
CMLCC_NB
PVI / SVID AM2 CPU
CMLCC COUT
SVI/PVI Interface
ST L6717 (3+1) Reference Schematic
Doc ID 17326 Rev 1
5/56
5 Page 
L6717
www.DataSheet4U.com
Pins description and connection diagrams
Table 2.
Pin#
25
26
27, 28
29
30
31
32
33
34
Pin description (continued)
Name
Function
SDA / OVP
SCL / OS
PWM4,
PWM3
VID5 /
ADDR
VID4 /
I2CDIS
SDA - power manager I2C data.
When power manager I2C is enabled, this is the data connection.
See Section 6 for details.
OVP - over voltage setting.
When power manager I2C is disabled (VID4 / I2CDIS to 3.3V) the pin is used to set
the OVP protection for CORE and NB sections. Define the OVP threshold by
connecting the pin to the center tap of a voltage divider from 3V3 to SGND.
See Section 8.1 for details.
SCL - power manager I2C clock.
When power manager I2C is enabled, this is the clock connection.
See Section 6 for details.
OS - CORE section offset.
When power manager I2C is disabled (VID4 / I2CDIS to 3.3V) this pin is internally set
to 1.24V(2.0V): connecting a ROS resistor to GND (3.3V) allows setting a current that
is mirrored into FB pin in order to program a positive (negative) offset according to the
selected RFB. Short to GND to disable the function. See Section 7.4 for details.
PWM output for external drivers.
Connect to external drivers PWM inputs. The device is able to manage HiZ status by
setting the pins floating.
By shorting to GND PWM4 or PWM3 and PWM4, it is possible to program the CORE
section to work at 3 or 2 phase respectively.
See Section 5.4.4 for details about HiZ management.
Voltage identification pin - I2C address pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI
mode, the pin is monitored on the EN pin rising-edge to modify the I2C address. See
Section 5 for details.
Voltage identification pin - I2C disable pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI
mode, the pin is monitored on the EN pin rising-edge to enable/disable the I2C. See
Section 5 for details.
Voltage IDentification Pin - SVI clock pin.
VID3 / SVC Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI
modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.
Voltage identification pins - SVI data pin.
VID2 / SVD Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI
modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.
Voltage identification pin.
VID1 / Internally pulled-low by 10μA, it programs the output voltage in PVI mode. The pin is
CORETYPE monitored on the EN pin rising-edge to define the operative mode of the controller
(SVI or PVI). See Section 5 for details.
Voltage identification pin.
VID0 / VFIX Internally pulled-low by 10μA, it programs the output voltage in PVI mode. If the pin is
pulled to 3.3V, the device enters V_FIX mode and SVI commands are ignored.
See Section 5 for details.
Doc ID 17326 Rev 1
11/56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L6717.PDF ] | |
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