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PDF IR3529 Data sheet ( Hoja de datos )
| Número de pieza | IR3529 | |
| Descripción | XPHASE3 PHASE IC | |
| Fabricantes | International Rectifier | |
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IR3529
DATA SHEET
XPHASE3TM PHASE IC
DESCRIPTION
The IR3529 Phase IC combined with an IR XPhase3TM Control IC provides a full featured and flexible way to
implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall
system control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a
multiphase converter. The XPhase3TM architecture results in a power supply that is smaller, less expensive, and
easier to design while providing higher efficiency than conventional approaches.
The IR3529 provides two types of current sense outputs; ILL which contains average power supply current,
information which can be used for voltage positioning and ISHARE which contains average active phase current
information since current sense amplifiers of respective phases are disabled when in power savings mode. Higher
efficiency can be expected due to increased driver capability along with reduced non-overlap durations. Turbo is
included to improve load turn-on response. A SHIFT pin now communicates to the control IC a change in phase
IC on-line status resulting in controlled phase timing during PSI and Phase Shedding. The IR3529 also
implements cycle-by-cycle over current protection to resolve high repetition rate load transients.
FEATURES
• Reduced dead time
• 7V gate drivers (6A GATEL sink current, 4A GATEH sink current)
• Turbo Mode load turn-on response enhancement
• Programmable cycle-by-cycle over current limit protection
• Phase status communicated to control IC for controlled phase timing during PSI and Phase Shedding
• Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads.
• Anti-bias circuitry
• Support converter output voltage up to 5.1 V (Limited to VCCL-1.8V)
• Loss-less inductor current sensing
• Phase delay DFF bypassed during PSI assertion mode to improve output ripple performance
• Over-current protection during PSI assertion mode operation
• Feed-forward voltage mode control
• Integrated boot-strap synchronous PFET
• Only four external components per phase
• 3 wire analog bus connects Control and Phase ICs (VID, Error Amp, Average Power Supply Current)
• 3 wire digital bus for accurate daisy-chain phase timing control without external components
• Debugging function isolates phase IC from the converter
• Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
• Single-wire bidirectional average current sharing
• Small thermally enhanced 20L 4 X 4mm MLPQ package
• RoHS compliant
Page 1 of 22
February 12, 2010
1 page  
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IR3529
PARAMETER
SW Floating Voltage
Calibrated Input Offset
Voltage
GAIN
Differential Input Range
Differential Input Range
Common Mode Input
Range
ILL Rout at TJ = 125 ºC
ISHARE Rout at TJ =125 ºC
Current Sense Amplifier
CSIN+/- Bias Current
SW Floating Voltage
Calibrated Input Offset
Voltage
Gain
Differential Input Range
Differential Input Range
Common Mode Input
Range
ILL Rout at TJ = 125 oC
ISHARE Rout at TJ =125 oC
Share Adjust Amplifier
Maximum PWM Ramp
Floor Voltage
Minimum PWM Ramp Floor
Voltage
Body Brake Comparator
Threshold Voltage with
EAIN decreasing
Threshold Voltage with
EAIN increasing
Hysteresis
Body Brake Comparator
Threshold Voltage with
EAIN decreasing
Threshold Voltage with
EAIN increasing
Hysteresis
TEST CONDITION
Measured in the application with the
converter not switching. Measure after 50us
of CLKIN=0 with CSINM shorted to SW
CSIN+ = CSIN- = DACIN. Measure input
referred offset from DACIN. Note1
0.5V ≤ V(DACIN) < 1.6V
0.8V ≤ V(DACIN) ≤ 1.6V, Note 1
0.5V ≤ V(DACIN) < 0.8V, Note 1
Note 1
I(CSINM) measured with I(CSINM) sink
turned off (i.e. within 8us of CLKIN fall and
EAIN above Body Brake Threshold and
CSINM above 75% DACIN)
Measured in the application with the
converter not switching. Measure after 50us
of CLKIN=0 with CSINM shorted to SW
CSIN+ = CSIN- = DACIN. Measure input
referred offset from DACIN. Note1
0.5V ≤ V(DACIN) < 1.6V
0.8V ≤ V(DACIN) ≤ 1.6V, Note 1
0.5V ≤ V(DACIN) < 0.8V, Note 1
Note 1
ISHARE = DACIN – 200mV. Measure
relative to floor voltage.
ISHARE = DACIN + 200mV. Measure
relative to floor voltage.
Measure relative to Floor Voltage
Measure relative to Floor Voltage
Measure relative to Floor Voltage
Measure relative to Floor Voltage
Page 5 of 22
MIN TYP MAX UNIT
10 100 250 mV
-450
+450 µV
31.0
-10
-5
0
3.6
3.6
32.5
4.7
4.7
34.5
50
50
VCCL
– 2.5V
5.4
5.4
V/V
mV
mV
V
kΩ
kΩ
-200 0
200 nA
10 100 250 mV
-450
+450 µV
31.0
-10
-5
0
3.6
3.6
32.5
4.7
4.7
34.5
50
50
VCCL
– 2.5V
5.4
5.4
V/V
mV
mV
V
kΩ
kΩ
120 180
-220 -160
240
-100
mV
mV
-300 -200
-200
70
-100
105
-110
-10
130
mV
mV
mV
-300 -200 -110
-200
70
-100
105
-10
130
February 12, 2010
mV
mV
mV
5 Page 
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IR3529
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
vL
iL L
RL
RCS
Current
Sense Amp
CSOUT
CCS
vCcS
VO
CO
Figure 4: Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being
delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage
can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the
inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no
information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation.
If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output
impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM
prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-
average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 4. Its gain is nominally
32.5, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping.
The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases
through an on-chip 3KΩ resistor connected to the ILL pin. The output of the current sense amplifier is summed with the
DAC voltage and sent to the phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ILL pins of all
the phases are tied together and the voltage on the share bus represents the average current through all the inductors
and is used by the control IC for voltage positioning. The ISHARE pins of all the phases are tied together and are not
connected to the control IC. The input offset of this amplifier is calibrated to +/- 1mV in order to reduce the current
sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on IOUT bus with a frequency of fsw/896 in a multiphase architecture.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The
output of the current sense amplifier is compared with the average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the
Page 11 of 22
February 12, 2010
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet IR3529.PDF ] | |
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