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PDF IR3521 Data sheet ( Hoja de datos )

Número de pieza IR3521
Descripción XPHASE3 AMD SVID CONTROL IC
Fabricantes International Rectifier 
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IR3521
DATA SHEET
XPHASE3TM AMD SVID CONTROL IC
DESCRIPTION
The IR3521 Control IC combined with an xPHASE3TM Phase IC provides a full featured and flexible way to
implement a complete AMD SVID power solution. It provides outputs for both the VDD core and VDDNB
auxiliary planes required by the CPU. The IR3521 provides overall system control and interfaces with any
number of Phase ICs each driving and monitoring a single phase. The xPHASE3TM architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
FEATURES
2 converter outputs for the AMD processor VDD core and VDDNB auxiliary planes
Supports High Speed (HS) I2C Serial communications
PSI_L serial commands are communicated to a programmable number of phase ICs
0.5% overall system set point accuracy
High speed error amplifiers with wide bandwidth of 20MHz and fast slew rate of 10V/us
Remote sense amplifiers provide differential sensing and require less than 50uA bias current
Programmable Dynamic VID Slew Rates
Programmable VID Offset (VDD output only)
Programmable output impedance (VDD output only)
Programmable Dynamic OC for IDD_Spike
Programmable per phase switching frequency of 250kHz to 1.5MHz
Hiccup over current protection with delay during normal operation
Central over voltage detection and communication to phase ICs through IIN (ISHARE) pin
OVP disabled during dynamic VID down to prevent false triggering
Over voltage signal to system with over voltage detection during powerup and normal operation
Detection and protection of open remote sense lines
Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
Small thermally enhanced 32L MLPQ (5mm x 5mm) package
ORDERING INFORMATION
Device
IR3521MTRPBF
IR3521MPBF (Samples Only)
Package
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ (5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
Page 1
V3.03

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IR3521 pdf
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IR3521
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied. All voltages are absolute voltages referenced to the
LGND pin.
Operating Junction Temperature……………..0 to 150oC
Storage Temperature Range………………….-65oC to 150oC
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
Reflow Temperature…………………………….260oC
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EPAD
PIN NAME
SVD
PWROK
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
VDAC1
SS/DEL1
IIN1
VDRP1
ROSC/OVP
PSI_L
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
PGOOD
SVC
LGND
VMAX
8V
8V
3.5V
8V
8V
3.5V
8V
8V
8V
8V
8V
1.0V
1.0V
8V
8V
8V
8V
8V
3.5V
8V
8V
8V
8V
VCCL+ 0.3V
8V
8V
8V
8V
3.5V
10V
VCCL + 0.3V
8V
n/a
VMIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
ISOURCE
1mA
1mA
1mA
5mA
1mA
1mA
1mA
25mA
1mA
5mA
5mA
5mA
5mA
5mA
5mA
1mA
25mA
1mA
1mA
1mA
5mA
35mA
1mA
1mA
100mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
20mA
ISINK
10mA
1mA
1mA
1mA
1mA
1mA
1mA
10mA
1mA
25mA
1mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
20mA
100mA
10mA
1mA
20mA
1mA
50mA
20mA
1mA
1mA
Page 5
V3.03

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IR3521 arduino
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IR3521
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the xPHASE3TM architecture is shown in Figure 4. Feed-forward voltage mode control
with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and
wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is
performed by the phase ICs as a result of sensing the input voltage (FET’s drain voltage). The PWM ramp slope
will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage
can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related
to changes in load current.
IR35121CONTROL IC
CLOCK GENERATOR
CLKOUT
PHSOUT
PHSIN
GATE DRIVE
VOLTAGE
REMOTE SENSE
AMPLIFIER
ERROR
AMPLIFIER
VDAC
IFB1
IROSC
VDRP1 AMP
Output 1 Only
VOUT1
VDAC1
LGND
EAOUT1
FB1
RCP1
CCP13
CCP14
RFB12
CFB2
RFB11
VDRP1
CDRP2 RDRP1
IIN1
PHSOUT
CLKIN
PHSIN
EAIN
IR3505 PHASE IC
CLK Q
D
PWM
LATCH
S
PWM
RESET
COMPARATOR DOMINANT
-R
+
ENABLE
VID6
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CBST
ISHARE
SHARE ADJUST
ERROR AMPLIFIER
VID6
- VID6
3K +
DACIN
VID6
VID6 +
+
CURRENT
SENSE
AMPLIFIER
CSIN+
CCS RCS
CSIN-
PHSOUT
CLKIN
PHSIN
EAIN
IR3505 PHASE IC
CLK Q
D
PWM
LATCH
S
PWM
RESET
COMPARATOR DOMINANT
-R
+
ENABLE
VID6
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CBST
ISHARE
SHARE ADJUST
ERROR AMPLIFIER
VID6
- VID6
3K +
DACIN
VID6
VID6 +
+
CURRENT
SENSE
AMPLIFIER
CSIN+
CCS RCS
CSIN-
VIN
VOSNS1+
VOUT1
COUT
GND
VOSNS1-
Figure 4 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator (system clock) is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an
external resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop. The control IC phase clock output (PHSOUT) is
connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to
complete the loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins
and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain
loop. Figure 5 shows the phase timing for a four phase converter.
Page 11
V3.03

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