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PDF MAX14548E Data sheet ( Hoja de datos )
| Número de pieza | MAX14548E | |
| Descripción | 16-Channel LLTs | |
| Fabricantes | Maxim Integrated Products | |
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19-5248; Rev 0; 4/10
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
100Mbps, 16-Channel LLTs
General Description
The MAX14548E/MAX14548AE 16-channel, bidirectional
level translators (LLTs) provide the level shifting neces-
sary for 100Mbps data transfer in multivoltage systems.
Externally applied voltages, VCC and VL, set the logic
levels on either side of the device. Logic signals present
on the VL side of the device appear as a high-voltage
logic signal on the VCC side of the device and vice versa.
The devices feature a programming frequency input (PF) that
adjusts the one-shot accelerator on-time to guarantee a bit
rate of 100Mbps with a load capacitance < 15pF and VL >
1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven
low. The MAX14548E can drive capacitive loads up to
50/R 1.1pF with a guaranteed bit rate of 40Mbps when
VL > 1.1/R 1.1V and PF is driven high. The MAX14548AE
can drive capacitive loads up to 50pF with a guaranteed
bit rate of 40Mbps when VL > 1.1V and PF is driven high.
The device operate at full speed with external drivers
that source as low as 4mA output current. Each I/O chan-
nel is pulled up to VCC or VL by an internal 35FA current
source, allowing both devices to be driven by either
push-pull or open-drain drivers.
The devices feature multiple power-saving features
including an enable input (EN) that places the device
into a low-power shutdown mode when driven low and
an automatic shutdown mode that disables the part
when VCC is less than VL. The MAX14548AE output driv-
er is designed to operate at full speed (100Mbps) with
VL > 1.4V, which reduces the dynamic supply current vs.
the MAX14548E. The state of I/O VCC_and I/O VL_are in
high-impedance state during shutdown.
The devices operate with VCC voltages from +1.7V to
+3.6V and VL voltages from +1.1V to +3.6V, making
them ideal for data transfer between low-voltage ASICs/
PLDs and higher voltage systems. The devices are avail-
able in a 40-bump WLP (2.16mm x 3.46mm) package
with 0.4mm ball pitch, and operate over the extended
-40NC to +85NC temperature range.
Features
S Bidirectional Level Translation
S 100Mbps Guaranteed Data Rate
S +1.7V to +3.6V Supply Voltage Range for VCC
S +1.1V to +3.6V Supply Voltage Range for VL
(VCC > VL)
S -40NC to +85NC Extended Operating Temperature
Range
Applications
CMOS Logic-Level Translation
Low-Voltage ASIC Level Translation
Smart Card Readers
Portable Communication Devices
Cell Phones
GPS
Telecommunications Equipment
Typical Operating Circuit appears at end of data sheet.
Ordering Information/Selector Guide
PART
PIN-
PACKAGE
BIT RATE (PF = LOW)
LOAD CAPACITANCE < 15pF
(Mbps)
BIT RATE (PF = HIGH)
LOAD CAPACITANCE < 50pF
(Mbps)
MAX14548EEWL+
MAX14548AEEWL+
40 WLP
40 WLP
100
100
40
40
Note: All devices operate over the -40°C to +85°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
LOW DYNAMIC
SUPPLY
CURRENT
—
Yes (VL > 1.1V)
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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100Mbps, 16-Channel LLTs
LOW-SPEED TIMING CHARACTERISTICS—MAX14548E
(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF,
TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER
I/O VCC_ Rise Time
I/O VCC_ Fall Time
I/O VL_ Rise Time
I/O VL_ Fall Time
Propagation Delay
(Driving I/O VL_)
Propagation Delay
(Driving I/O VCC_)
Channel-to-Channel Skew
Propagation Delay from
I/O VL_ to I/O VCC_ After EN
Propagation Delay from
I/O VCC_ to I/O VL_ After EN
Maximum Data Rate
SYMBOL
tRVCC
tFVCC
tRVL
tFVL
tPVL-VCC
tPVCC-VL
tSKEW
tEN-VCC
tEN-VL
CONDITIONS
Input rise time < 6ns, Figure 1
Input fall time < 6ns, Figure 1
Input rise time < 6ns, Figure 2
Input rise time < 6ns, Figure 2
Input rise time < 6ns, Figure 1
Input rise time < 6ns, Figure 2
Input rise time/fall time < 6ns
RLOAD = 1MI, Figure 3
RLOAD = 1MI, Figure 3
Push-pull operation
Open-drain operation
MIN TYP MAX UNITS
6 ns
6 ns
6 ns
6 ns
4 ns
3.37
0.2
27
0.5
ns
ns
Fs
0.06
40
0.3
Fs
Mbps
LOW-SPEED TIMING CHARACTERISTICS—MAX14548AE
(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF,
TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER
I/O VCC_ Rise Time
I/O VCC_ Fall Time
I/O VL_ Rise Time
I/O VL_ Fall Time
Propagation Delay
(Driving I/O VL_)
SYMBOL
tRVCC
tFVCC
tRVL
tFVL
tPVL-VCC
CONDITIONS
Input rise time < 6ns, Figure 1
Input fall time < 6ns, Figure 1
Input rise time < 6ns, Figure 2
Input rise time < 6ns, Figure 2
Input rise time < 6ns, Figure 1
MIN TYP MAX UNITS
6 ns
6 ns
6 ns
6 ns
4 ns
Propagation Delay
(Driving I/O VCC_)
Channel-to-Channel Skew
Propagation Delay from
I/O VL_ to I/O VCC_ After EN
tPVCC-VL
tSKEW
tEN-VCC
Input rise time < 6ns, Figure 2
Input rise time/fall time < 6ns
RLOAD = 1MI, Figure 3
3.37
0.2
27
ns
ns
Fs
Propagation Delay from
I/O VCC_ to I/O VL_ After EN
Maximum Data Rate
tEN-VL
RLOAD = 1MI, Figure 3
Push-pull operation
Open-drain operation
0.06
40
0.3
Fs
Mbps
Note 2: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design and not production tested.
Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 4: When VCC is below VL by more than the VL - VCC shutdown threshold, the device turns off its pullup generators and
I/O VCC_ and I/O VL_ enter their respective shutdown states.
Note 5: Guaranteed by design.
Note 6: Input thresholds are referenced to the boost circuit.
5
5 Page 
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100Mbps, 16-Channel LLTs
Pin Configuration
TOP VIEW
(BUMPS ON BOTTOM)
MAX14548E
MAX14548AE
12345678
+
A
I/O VL1 I/O VL2 I/O VL3 I/O VL4 I/O VL5 I/O VL6 I/O VL7 I/O VL8
B
I/O VL9 I/O VL10 I/O VL11 I/O VL12 I/O VL13 I/O VL14 I/O VL15 I/O VL16
C
GND VL VCC EN PF VCC VL GND
D
I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 I/O VCC5 I/O VCC6 I/O VCC7 I/O VCC8
E
I/O VCC9 I/O VCC10 I/O VCC11 I/O VCC12 I/O VCC13 I/O VCC14 I/O VCC15 I/O VCC16
WLP
(2.16mm × 3.46mm)
PIN
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1, C8
NAME
I/O VL1
I/O VL2
I/O VL3
I/O VL4
I/O VL5
I/O VL6
I/O VL7
I/O VL8
I/O VL9
I/O VL10
I/O VL11
I/O VL12
I/O VL13
I/O VL14
I/O VL15
I/O VL16
GND
Input/Output 1. Referenced to VL.
Input/Output 2. Referenced to VL.
Input/Output 3. Referenced to VL.
Input/Output 4. Referenced to VL.
Input/Output 5. Referenced to VL.
Input/Output 6. Referenced to VL.
Input/Output 7. Referenced to VL.
Input/Output 8. Referenced to VL.
Input/Output 9. Referenced to VL.
Input/Output 10. Referenced to VL.
Input/Output 11. Referenced to VL.
Input/Output 12. Referenced to VL.
Input/Output 13. Referenced to VL.
Input/Output 14. Referenced to VL.
Input/Output 15. Referenced to VL.
Input/Output 16. Referenced to VL.
Ground
FUNCTION
Pin Description
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MAX14548E.PDF ] | |
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