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PDF SC16IS741 Data sheet ( Hoja de datos )

Número de pieza SC16IS741
Descripción Single UART with I2C-bus/SPI interface
Fabricantes NXP Semiconductors 
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SC16IS741
Single UART with I2C-bus/SPI interface, 64 bytes of transmit
and receive FIFOs, IrDA SIR built-in support
Rev. 01 — 29 April 2010
Product data sheet
1. General description
The SC16IS741 is a slave I2C-bus/SPI interface to a single-channel high performance
UART. It offers data rates up to 5 Mbit/s and guarantees low operating and sleeping
current. The device comes in the TSSOP16 package, which makes it ideally suitable for
handheld, battery operated applications. This device enables seamless protocol
conversion from I2C-bus or SPI to and RS-232/RS-485 and are fully bidirectional.
The SC16IS741’s internal register set is backward-compatible with the widely used and
widely popular 16C450. This allows the software to be easily written or ported from
another platform.
The SC16IS741 also provides additional advanced features such as auto hardware and
software flow control, automatic RS-485 support, and software reset. This allows the
software to reset the UART at any moment, independent of the hardware reset signal.
2. Features
2.1 General features
„ Single full-duplex UART
„ Selectable I2C-bus or SPI interface
„ 3.3 V or 2.5 V operation
„ Industrial temperature range: 40 °C to +95 °C
„ 64 bytes FIFO (transmitter and receiver)
„ Fully compatible with industrial standard 16C450 and equivalent
„ Baud rates up to 5 Mbit/s in 16× clock mode
„ Auto hardware flow control using RTS/CTS
„ Auto software flow control with programmable Xon/Xoff characters
„ Single or double Xon/Xoff characters
„ Automatic RS-485 support (automatic slave address detection)
„ RS-485 driver direction control via RTS signal
„ RS-485 driver direction control inversion
„ Built-in IrDA encoder and decoder interface
„ Software reset
„ Transmitter and receiver can be enabled/disabled independent of each other
„ Receive and Transmit FIFO levels
„ Programmable special character detection

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SC16IS741 pdf
NXP Semiconductors
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SC16IS741
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 2.
Symbol
VSS
RTS
CTS
TX
RX
RESET
XTAL1
XTAL2
Pin description …continued
Pin Type Description
9-
ground
10 O
UART request to send (active LOW). A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing a
logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin is set to a
logic 1. This pin only affects the transmit and receive operations when
auto RTS function is enabled via the Enhanced Feature Register
(EFR[6]) for hardware flow control operation.
11 I
UART clear to send (active LOW). A logic 0 (LOW) on the CTS pin
indicates the modem or data set is ready to accept transmit data from
the SC16IS741. Status can be tested by reading MSR[4]. This pin
only affects the transmit and receive operations when auto CTS
function is enabled via the Enhanced Feature Register EFR[7] for
hardware flow control operation.
12 O
UART transmitter output. During the local Loopback mode, the TX
output pin is disabled and TX data is internally connected to the
UART RX input.
13 I
UART receiver input. During the local Loopback mode, the RX input
pin is disabled and TX data is connected to the UART RX input
internally.
14 I
device hardware reset (active LOW)[1]
15 I
Crystal input or external clock input. Functions as a crystal input or as
an external clock input. A crystal can be connected between XTAL1
and XTAL2 to form an internal oscillator circuit (see Figure 11).
Alternatively, an external clock can be connected to this pin.
16 O
Crystal output or clock output. (See also XTAL1.) XTAL2 is used as a
crystal oscillator output.
[1] See Section 7.4 “Hardware reset, Power-On Reset (POR) and software reset”
7. Functional description
SC16IS741_1
Product data sheet
The UART will perform serial-to-I2C conversion on data characters received from
peripheral devices or modems, and I2C-to-serial conversion on data characters
transmitted by the host. The complete status the SC16IS741 UART can be read at any
time during functional operation by the host.
The SC16IS741 can be placed in an alternate mode (FIFO mode) relieving the host of
excessive software overhead by buffering received/transmitted characters. Both the
receiver and transmitter FIFOs can store up to 64 characters (including three additional
bits of error status per character for the receiver FIFO) and have selectable or
programmable trigger levels.
The SC16IS741 has selectable hardware flow control and software flow control. Hardware
flow control significantly reduces software overhead and increases system efficiency by
automatically controlling serial data flow using the RTS output and CTS input signals.
Software flow control automatically controls data flow by using programmable Xon/Xoff
characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (216 – 1).
Rev. 01 — 29 April 2010
© NXP B.V. 2010. All rights reserved.
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SC16IS741
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.5 Interrupts
The SC16IS741 has interrupt generation and prioritization capability. The Interrupt Enable
Register (IER) enables each of the interrupts and the IRQ signal in response to an
interrupt generation. When an interrupt is generated, the IIR indicates that an interrupt is
pending and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the
interrupt control functions.
Table 6.
IIR[5:0]
00 0001
00 0110
00 1100
00 0100
00 0010
00 0000
01 0000
10 0000
Summary of interrupt control functions
Priority Interrupt type
level
Interrupt source
none
none
none
1 receiver line status OE, FE, PE, or BI errors occur in characters in the
RX FIFO
2 RX time-out
Stale data in RX FIFO
2
RHR interrupt
Receive data ready (FIFO disable) or
RX FIFO above trigger level (FIFO enable)
3 THR interrupt Transmit FIFO empty (FIFO disable) or
TX FIFO passes above trigger level (FIFO enable)
4
Modem status
Change of state of modem input pins
6 Xoff interrupt
Receive Xoff character(s)/ special character
7 CTS, RTS
RTS pin or CTS pin change state from active (LOW)
to inactive (HIGH)
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
SC16IS741_1
Product data sheet
Rev. 01 — 29 April 2010
© NXP B.V. 2010. All rights reserved.
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