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PDF MAX11645 Data sheet ( Hoja de datos )

Número de pieza MAX11645
Descripción 2-Wire Serial 12-Bit ADCs
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! MAX11645 Hoja de datos, Descripción, Manual

19-5225; Rev 0; 4/10
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EVAALVUAAILTAIOBNLEKIT
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
General Description
The MAX11644/MAX11645 low-power, 12-bit, 1-/2-
channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and
an I2C-compatible 2-wire serial interface. These
devices operate from a single supply of 2.7V to 3.6V
(MAX11645) or 4.5V to 5.5V (MAX11644) and require
only 670µA at the maximum sampling rate of 94.4ksps.
Supply current falls below 230µA for sampling rates
under 40ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current
to less than 1µA at low throughput rates. The
MAX11644/MAX11645 each measure two single-ended
or one differential input. The fully differential analog
inputs are software configurable for unipolar or bipolar,
and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11645 fea-
tures a 2.048V internal reference and the MAX11644
features a 4.096V internal reference.
The MAX11644/MAX11645 are available in an 8-pin
µMAX® package. The MAX11644/MAX11645 are guar-
anteed over the extended temperature range (-40°C to
+85°C). For pin-compatible 10-bit parts, refer to the
MAX11646/MAX11647 data sheet.
Handheld Portable
Applications
Medical Instruments
Battery-Powered Test
Equipment
Solar-Powered Remote
Systems
Applications
Received-Signal-Strength
Indicators
System Supervision
Power-Supply Monitoring
Features
o High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single-Supply
2.7V to 3.6V (MAX11645)
4.5V to 5.5V (MAX11644)
o Internal Reference
2.048V (MAX11645)
4.096V (MAX11644)
o External Reference: 1V to VDD
o Internal Clock
2-Channel Single-Ended or 1-Channel Fully
Differential
o Internal FIFO with Channel-Scan Mode
o Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
o Software-Configurable Unipolar/Bipolar
o Small, 8-Pin µMAX Package
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
I2C SLAVE
ADDRESS
MAX11644EUA+ -40°C to +85°C 8 µMAX
0110110
MAX11645EUA+ -40°C to +85°C 8 µMAX
0110110
+Denotes a lead(Pb)-free/RoHs-compliant package.
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
AutoShutdown is a trademark and µMAX is a registered trademark
of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

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MAX11645 pdf
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1 Measured from 0.3VDD - 0.7VDD
20 160 ns
Fall Time of SCL Signal
tFCL Measured from 0.3VDD - 0.7VDD
20 80 ns
Rise Time of SDA Signal
tRDA Measured from 0.3VDD - 0.7VDD
20 160 ns
Fall Time of SDA Signal
tFDA Measured from 0.3VDD - 0.7VDD (Note 11)
20
160 ns
Setup Time for STOP Condition
tSU, STO
160 ns
Capacitive Load for Each Bus Line CB
400 pF
Pulse Width of Spike Suppressed
tSP (Notes 10 and 13)
0 10 ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
For DC accuracy, the MAX11644 is tested at VDD = 5V and the MAX11645 is tested at VDD = 3V with an external
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Offset nulled.
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to VDD.
When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1µF capacitor and a 2kseries resistor (see the Typical Operating Circuit).
ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Measured for the MAX11645 as:
⎢⎡⎣VFS
⎣⎢
(3.6V)
VFS (2.7V)⎤⎦
×
2N
VREF
⎦⎥
(3.6V 2.7V)
and for the MAX11644, where N is the number of bits:
⎣⎢⎢⎡⎣VFS (5.5V)
VFS
(4.5V)⎤⎦
×
2N
VREF
⎦⎥
(5.5V 4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 11: The minimum value is specified at TA = +25°C.
Note 12: CB = total capacitance of one bus line in pF.
Note 13: fSCL must meet the minimum clock low time plus the rise/fall times.
_______________________________________________________________________________________ 5

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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Analog Input Range and Protection
Internal protection diodes clamp the analog input to VDD
and GND. These diodes allow the analog inputs to swing
from (GND - 0.3V) to (VDD + 0.3V) without causing dam-
age to the device. For accurate conversions, the inputs
must not go more than 50mV below GND or above VDD.
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX11644/MAX11645 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS[0] and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[0] (Table 4).
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is bina-
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11644/MAX11645
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX11644/MAX11645 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock
line (SCL). SDA and SCL facilitate bidirectional commu-
nication between the MAX11644/MAX11645 and the
master at rates up to 1.7MHz. The MAX11644/
MAX11645 are slaves that transfer and receive data.
The master (typically a microcontroller) initiates data
transfer on the bus and generates the SCL signal to
permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750or greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional. They
protect the input architecture of the MAX11644/
MAX11645 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11644/MAX11645.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START (S)
condition, a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP
(P) condition, a low-to-high transition on SDA while SCL
is high (Figure 5). A repeated START (Sr) condition
can be used in place of a STOP condition to leave the
bus active and the interface mode unchanged (see the
HS Mode section).
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11644/MAX11645 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
S Sr
P
SDA
SCL
Figure 5. START and STOP Conditions
S
SDA
SCL
12
NOT-ACKNOWLEDGE
ACKNOWLEDGE
89
Figure 6. Acknowledge Bits
______________________________________________________________________________________ 11

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