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PDF SAA6703H Data sheet ( Hoja de datos )
| Número de pieza | SAA6703H | |
| Descripción | Xga Dual Input Flat Panel Controller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
SAA6703H
XGA dual input flat panel controller
Product specification
2004 Apr 01
1 page  
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VSSA(BIAS)(B) VSSA(BIAS)(R) VDDA(ADC)(G) VSSA(ADC)(B) VSSA(ADC)(R) CSG4/A1 SDA
VSSA(BIAS)(G) VDDA(ADC)(B) VDDA(ADC)(R) VSSA(ADC)(G)
CSG2/A0 SCL
TCK
TDI
HSDA HSCL TRST TMS TDO RST INT
CLK
VCLK
AGCANA
HSYNC
VSYNC
SOGIN
RXCP, RXCN
RX0P, RX0N
RX1P, RX1N
RX2P, RX2N
RIN
GIN
BIN
RBIAS
REF_B
REF_G
REF_R
1
47
135
160
141
140
11
37, 36
33, 34
30, 31
27, 28
20
13
2
9
4
15
22
12 19 3
14 21
CLOCK GENERATOR:
PANEL CLOCK PLL
SAMPLE CLOCK PLL
PHASE SHIFT
syncs
SYNC-
ON-
GREEN
SLICER
syncs
data
enable
SYNC
SELECTION
AND CSYNC
DECODER
DVI 1.0
INTERFACE
3 × ADC
syncs
HDCP
RGB
data
3 × 8-bit
INPUT
INTERFACE
RGB data
3 × 8-bit
RGB data
3 × 8-bit
5 16 23 55 127 42 41 43 44
panel clock
sample clock
I2C-BUS
INTERFACE 1
configuration
data
I2C-BUS
INTERFACE 2
HDCP
data
syncs
MODE
DETECTION
SAA6703H
AUTO-
ADJUSTMENT
RGB data
3 × 8-bit DOWN-
SCALER
DECOUPLING
FIFO
UPSCALER
OSD
COLOUR
LOOK-UP
TABLE
RGB data
3 × 10-bit
DITHERING
153 154 156 155 157 51 50
JTAG
INTERFACE
test control
signals
39
40
6
17
24
7
18
25
CONTROL
UNIT
46, 71, 91,
103, 123,
145
control signals
45, 70, 90,
102, 122, 144
panel control
signals
52
53, 54, 126
138, 139
OUTPUT
INTERFACE
RGB data
3 × 6-bit or
3 × 8-bit
58 to 65,
68, 69,
72 to 77,
80 to 87
RGB data
3 × 6-bit or
3 × 8-bit
RGB data 92 to 99,
3 × 6-bit or 104 to 111,
3 × 8-bit 114 to 121
128, 129,
26, 32,
136, 137, 130, 133,
10 8 38 29 35 148
134
48, 56, 66, 78,
88, 100, 112,
124, 131, 142
49, 57, 67, 79,
89, 101, 113,
125, 132, 143
159 158 146
147 149 150 152 151
VDDA(IB)
VSSA(DVI1)
n.c.
VSSA(BIAS)(SOG) VDDA(DVI1) to
VDDA(DVI3)
VSSA(DVI2)
RESERVED1 to
RESERVED5
VSSD(EP1) to
VSSD(EP10)
VDDD(EP1) to
VDDD(EP10)
VDDA(EP)
VSS(PLL)(P) VSSA(PLL)(S) VDDD(PLL)(S)
VSSA(EP)
VDD(PLL)(P) VDDA(PLL)(S) VSSD(PLL)(S)
VSS(PLL)(DVI)
VDD(PLL)(DVI)
VDDA(B)
VDDA(G)
VDDA(R)
VSSA(B)
VSSA(G)
VSSA(R)
VDDD(IC1) to
VDDD(IC6)
VSSD(IC1) to
VSSD(IC6)
PCLK
CSG0, CSG1,
CSG3
OUTEN, PWM
PA0 to PA7,
PB0 to PB7,
PC0 to PC7
PD0 to PD7,
PE0 to PE7,
PF0 to PF7
001aaa176
Fig.1 Block diagram.
5 Page 
Philips Semiconductors
XGA dual input flat panel controller
www.DataSheet4U.com
Product specification
SAA6703H
VSSA(BIAS)(B)
BIN
VDDA(ADC)(B)
REF_B
VSSA(ADC)(B)
VDDA(B)
VSSA(B)
VDDA(IB)
RBIAS
VSSA(BIAS)(SOG)
SOGIN
VSSA(BIAS)(G)
GIN
VDDA(ADC)(G)
REF_G
VSSA(ADC)(G)
VDDA(G)
VSSA(G)
VSSA(BIAS)(R)
RIN
VDDA(ADC)(R)
REF_R
VSSA(ADC)(R)
VDDA(R)
VSSA(R)
VDDA(DVI1)
RX2P
RX2N
VSSA(DVI1)
RX1P
RX1N
VDDA(DVI2)
RX0P
RX0N
VSSA(DVI2)
RXCN
RXCP
VDDA(DVI3)
VSS(PLL)(DVI)
VDD(PLL)(DVI)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
2004 Apr 01
SAA6703H
Fig.2 Pin configuration.
11
120 PF6
119 PF5
118 PF4
117 PF3
116 PF2
115 PF1
114 PF0
113 VDDD(EP7)
112 VSSD(EP7)
111 PE7
110 PE6
109 PE5
108 PE4
107 PE3
106 PE2
105 PE1
104 PE0
103 VDDD(IC4)
102 VSSD(IC4)
101 VDDD(EP6)
100 VSSD(EP6)
99 PD7
98 PD6
97 PD5
96 PD4
95 PD3
94 PD2
93 PD1
92 PD0
91 VDDD(IC3)
90 VSSD(IC3)
89 VDDD(EP5)
88 VSSD(EP5)
87 PC7
86 PC6
85 PC5
84 PC4
83 PC3
82 PC2
81 PC1
cok003
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet SAA6703H.PDF ] | |
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