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PDF LFXP20 Data sheet ( Hoja de datos )

Número de pieza LFXP20
Descripción LatticeXP Family
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! LFXP20 Hoja de datos, Descripción, Manual

LatticeXP Family Data Sheet
DS1001 Version 05.1, November 2007
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1 page




LFXP20 pdf
Lattice Semiconductor
Figure 2-1. LatticeXP Top Level Block Diagram
Programmable I/O Cell
(PIC) includes sysIO
Interface
Non-volatile Memory
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
Architecture
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LatticeXP Family Data Sheet
sysMEM Embedded
Block RAM (EBR)
JTAG Port
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
PFU and PFF Blocks
The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
Slice 3
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
To
Routing
2-2

5 Page





LFXP20 arduino
Lattice Semiconductor
Figure 2-6. Secondary Clock Sources
From
Routing
From
Routing
Clock
Input
Architecture
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LatticeXP Family Data Sheet
From
Routing
From
Routing
From Routing
From Routing
Clock Input
From Routing
From Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
Clock Input
From Routing
From Routing
From
Routing
From
Routing
Clock
Input
From
Routing
From
Routing
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
DCS2
DCS2
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.
2-8

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