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PDF MAD4868A Data sheet ( Hoja de datos )
| Número de pieza | MAD4868A | |
| Descripción | Micronas Audio Delay | |
| Fabricantes | Micronas | |
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MICRONAS
PRELIMINARY DATA SHEET
MAD 4868A
Micronas Audio Delay
Edition May 11, 2004
6251-636-1PD
MICRONAS
1 page  
PRELIMINARY DATA SHEET
MAD 4868A
www.DataSheet4U.com
2. Functional Description
2.1. Block Diagram
In Fig. 2–1, a simplified block diagram of the IC is
given. Between 1 and 8 channels can be delayed indi-
vidually by a programmable number of samples nx.
The delay RAM offers, depending on the accumulated
adjusted delay, a word width of 32 or 18 bits.
The accumulated delay must not exceed 7FF0hex
(32752dec) samples (i.e. 682 ms @ 48 kHz Fs). As the
bit clock (I2S_DEL_CL) is limited to 12.288 MHz and
the used I2S bus format has a fixed word length of 32
bit, the maximum sample rate fs is 192 kHz in parallel
mode (2-channels per data line) and 48 kHz in serial
mode (8-channels on I2S_DEL_IN1/OUT1).
2.2. I2S Bus Interface
The MAD 4868A has four I2S data input lines and four
I2S data output lines which together with I2S_DEL_WS
and I2S_DEL_CL form one I2S bus interface for vari-
ous sample rates in serial (8-channel) or parallel (2-
channel) mode. The I2S_DEL_CL, I2S_DEL_WS, and
I2S_DEL_IN1...4 are inputs to the MAD 4868A
(tristate) while I2S_DEL_OUT1...4 are outputs. Bit[1:0]
of the CONTROL register set the output driver active
or tristate and its strength to weak or strong (see
Table 3–3 on page 10). The interface works only in
synchronous slave mode and with a fixed wordlength
of each audio sample of 32 bits. Two different opera-
tional modes can be adjusted as described in the fol-
lowing sections.
Frame Clock (WS)
Input
Buffers
D1
D2
D3
2..8 D4
DI
D5
D6
D7
D8
0ms
[t1]
[t2]
[t3]
[t4]
[t5]
[t6]
[t7]
[t8]
Output
Buffers
D1
D2
D3
D4
D5
D6
D7
D8
2..8
DO
CONTROL[1:0]
Output Driver Active
Output Driver Strength
CONTROL[9:2]
Output Data Mute
unsoetd
680ms@48kHz
Fig. 2–1: Simplified block diagram of the MAD 4868A
Micronas
May 11, 2004; 6251-636-1PD
5
5 Page 
PRELIMINARY DATA SHEET
MAD 4868A
www.DataSheet4U.com
Table 3–3: User Interface, continued
Sub -
Address
(hex)
01hex...
08hex
Function
Mode
Channel Delay
The delay time tms in milliseconds; Delay nx must be calculated
and set as number of samples:
nx = (tms(x) × fs) -1
bit[15:0] nx
x = 1..8; n = 0..32752
number of delayed samples for channel x,
x = 1...8
example:
samples: nx
min delay 0
fs =
32 kHz
31 µs
fs =
48 kHz
21 µs
fs =
96 kHz
10 µs
fs =
192 kHz
5 µs
1Fhex 1.00 ms
2Fhex 1.50 ms
5Fhex 3.00 ms
...
max delay1) 7FF0hex 1023 ms
0.66 ms
1.00 ms
2.00 ms
682 ms
0.33 ms
0.50 ms
1.00 ms
341 ms
0.16 ms
0.25 ms
0.50 ms
170 ms
1) Since there are 32 KWords of RAM accessible, the SUM(n1:n8)
must be less than 7FF0hex (e.g. in total a maximum delay of
682 ms at a 48 kHz sample rate must not be exceeded).
Reset
Value
(hex)
0000hex
Name
CH1_DELAY
CH2_DELAY
CH3_DELAY
CH4_DELAY
CH5_DELAY
CH6_DELAY
CH7_DELAY
CH8_DELAY
Micronas
May 11, 2004; 6251-636-1PD
11
11 Page | ||
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