PDF ICSSSTU32866 Data sheet ( Hoja de datos )

Número de pieza	ICSSSTU32866
Descripción	25-Bit Configurable Registered Buffer
Fabricantes	Integrated Circuit System
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No Preview Available ! Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM logic solution with ICS97U877 Product Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSR# and RESET# inputs • Low voltage operation VDD = 1.7V to 1.9V • Available in 96 BGA package Functionality Truth Table I nputs Outp uts RST# DCS# CSR# CK CK# Dn, DODT, DCK E Qn QCS# QODT, QCKE HLL LL LL HLL HHL H H L L L or H L or H X Q0 Q0 Q0 HLH LL LL HLH HHL H H L H L or H L or H X Q0 Q0 Q0 HHL LL HL HHL HHHH H H L L or H L or H X Q0 Q0 Q0 HHH L Q0 H L HHH H Q0 H H H H H L or H L or H X Q0 Q0 Q0 L X or X or X or X or X or Floating Floating Floating Floating Floating L L L ICSSSTU32866 Advance Information www.DataSheet4U.com Pin Configuration 123456 A B C D E F G H J K L M N P R T 96 Ball BGA (Top View) 0850—08/27/03 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. 1 page ICSSSTU32866 Advance Inwfowwr.mDaatatSihoeent4U.com Block Diagram for 1:1 mode (positive logic) RST# CK CK# VREF DCKE DODT DCS# CSR# D C1 R D C1 R 1D C1 R QCKEA QODTA QCSA# D1 0 1 0850—08/27/03 To 21 Other Channels Note: Disabled in 1:1 configuration 5 1D C1 R Q1A Q1B 5 Page ICSSSTU32866 Advance Inwfowwr.mDaatatShioeent4U.com CK Inputs td = 350ps TL=50Ω Test Point RL = 100Ω Test Point DUT TL=350ps, 50Ω CK# Out CK CL = 30 pF (see Note 1) LOAD CIRCUIT VDD RL = 1000Ω Test Point RL = 1000Ω VCMOS RST# Inp ut t in act VDD/2 VDD/2 VDD 0V tact CK VICR CK VICR VID IDD (see Note 2) 10% 90% VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES tw VID tPLH tPHL Ou t put VTT VTT VOH VOL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES Inpu t VICR VICR VOLTAGE WAVEFORMS – PULSE DURATION VID CK VICR CK LVCMOS RST# In put VDD/2 VIH VIL tRPHL tsu th Inpu t VREF VREF VIH VIL VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES Ou t p u t VOH VTT VOL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES Figure 6 — Parameter M easurement I nfor mation (VDD = 1.8 V ± 0.1 V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM. 0850—08/27/03 11 11 Page

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