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PDF TDA21301 Data sheet ( Hoja de datos )
| Número de pieza | TDA21301 | |
| Descripción | Multi-Phase PWM Controller | |
| Fabricantes | Infineon Technologies | |
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Version 1.02 , Aug 2004
Datasheet
DS-CoreControl-TDA21301
TDA21301
Authors:
Edward Chang
Published by Infineon Technologies AG
http://www.infineon.com/DCDC
www.DataSheet4U.com
Power Management & Supply
CoreControl TM
N e v e r s t o p t h i n k i n g.
Page 1 of 25
DS-CoreControl-TDA21301
1 page  
General Description
www.DataSheet4U.com
TDA21301 is a multi-phase DC-DC buck converter controller integrated all control functions for the next generation GHz CPU
voltage regulator. TDA21301 automatically controls 2 to 4 interleaved buck switching power stage operation. The multi-phase
architecture is able to provide high output current with lower power dissipation on the switching devices and minimizing the
input ripple current and output ripple voltage. The equivalent high operation frequency optimizes the voltage regulator design
for better transient response and thermal performance.
TDA21301 utilizes the DCR of the output inductors in every channel as the current sense element. The differential current
sense in every channel results precious channel current information to the controller for good droop adjustment, channel
current balance, channel switching devices thermal balance and over current protection. The offset error caused by individual
differential current sense amplifier can be eliminated due to that the multiplexer is use to select the different channel current
sense signals with single differential current sense amplifier.
Block Diagram
VID0
VID1
VID2
VID3
VIDV1I2D54
VID DAC
& Step
Control
VOSS
Offset
Setting
OVP
Setting
PG
Setting
+
I
VCORE
FB COMP
PGOOD VCC
OVP DVD
Power On
Reset
RT
Oscillatior &
Sawtooth
++
+
I
INH ++
+
I
++
OCP
Setting
++
INH
+ PWM Logic
I
PWM CMP
INH
+ PWM Logic
I
PWM CMP
INH
+ PWM Logic
I
PWM CMP
INH
+ PWM Logic
I
PWM CMP
Current
Correction
Phase Control
Soft
Start
SS
ADJ
SUM/M
PWM1
PWM2
PWM3
PWM4
CSP1
CSP2
CSP3
CSP4
CSN
CoreControl TM
Page 5 of 25
DS-CoreControl-TDA21301
5 Page 
Application Information :
www.DataSheet4U.com
TDA21301 is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances
the current of different power channels. The converter consisting of TDA21301 and its companion
CoreControlTM drivers, provides high quality CPU core power and all the protection functions to meet the
requirement of the latest CPUs.
Voltage Control
The TDA21301 senses the CPU VCORE by SGND pin via a resistor connecting to Vss_sense pin of CPU
and by FB pin via a resistor connecting to Vcc-sense of CPU to achieve the on-die voltage sense and to
minimize the voltage drop on the PCB traces at heavy load condition. FB pin is also the input of the
PGOOD & OVP sense. The internal highly accurate VID DAC provides the reference voltage for
VRD10.X compliance. Control loop consists of an error amplifier, a pulse width modulator, external
driver ICs and power elements. As a conventional voltage mode controller, the output voltage is locked
at the VREF of the error amplifier which is the output voltage of VID DAC plus setting offset and droop
and the error signal is used as the control signal, Vc of the pulse width modulator. The PWM signals at
different channels are generated by comparison of EA output and split-phase saw-tooth wave with
additional current signal to achieve the balance current at each channel. Power stage transforms VIN to
output by PWM signal on-time ratio.
VID0
VID1
VID2
VID3
VIDV1I2D54
VID DAC
& Step
Control
VOSS
Offset
Setting
OVP
Setting
PG
Setting
+
I
PGOOD VCC
OVP DVD
Power On
Reset
RT
Oscillatior &
Sawtooth
+ INH
I
+
I
OCP
Setting
++
++
++
++
INH
+ PWM Logic
I
PWM CMP
INH
+ PWM Logic
I
PWM CMP
INH
+ PWM Logic
I
PWM CMP
INH
+ PWM Logic
I
PWM CMP
Current
Correction
Phase Control
PWM1
PWM2
PWM3
PWM4
CSP1
CSP2
CSP3
CSP4
CSN
Soft
Start SUM/M
VCORE
FB COMP
SS ADJ
CoreControl TM
Page 11 of 25
DS-CoreControl-TDA21301
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet TDA21301.PDF ] | |
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