PDF CBTL06121 Data sheet ( Hoja de datos )

Número de pieza	CBTL06121
Descripción	Gen1 hex display multiplexer
Fabricantes	NXP Semiconductors
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No Preview Available ! CBTL06121 Gen1 hex display multiplexer Rev. 01 — 23 May 2008 www.DataSheet4U.com Product data sheet 1. General description The CBTL06121 is a six-channel (‘hex’) multiplexer for DisplayPort and PCI Express applications at Generation 1 (‘Gen1’) speeds. It provides four differential channels capable of switching or multiplexing (bidirectional and AC-coupled) PCI Express or DisplayPort signals, using high-bandwidth pass-gate technology. Additionally, it provides for switching/multiplexing of the Hot Plug Detect signal as well as the AUX or DDC (Direct Display Control) signals, for a total of six channels. The CBTL06121 is designed for Gen1 speeds, at 2.5 Gbit/s for PCI Express or 2.7 Gbit/s for DisplayPort. The device is available in two different pinouts (A and B, orderable as separate part numbers) to suit different motherboard layout requirements. The typical application of CBTL06121 is on motherboards, docking stations or add-in cards where the graphics and I/O system controller chip utilizes I/O pins that are conﬁgurable for either PCI Express or DisplayPort operation. The hex display MUX can be used in such applications to route the signal from the controller chip to either a physical DisplayPort connector or a PCI Express connector using its 1 : 2 multiplexer topology. The controller chip selects which path to use by setting a select signal (which can be latched) HIGH or LOW. Optionally, the hex MUX device can be used in conjunction with an HDMI/DVI level shifter device (PTN3300A, PTN3300B or PTN3301) to allow for DisplayPort as well as HDMI/DVI connectivity. 1 page NXP Semiconductors 5. Functional diagram CBTL06121 www.DataSheet4U.com Gen1 hex display multiplexer MULTI-MODE DISPLAY SOURCE PCIe PHY ELECTRICAL PCIe output buffer TX PCIe output buffer TX PCIe output buffer TX PCIe output buffer TX PCIe input buffer RX PCIe input buffer RX TX Fig 4. Functional diagram CBTL06121_1 Product data sheet SEL LE_N MUX LOGIC XSD AC-coupled differential pair IN_0+ DATA LANE IN_0− AC-coupled differential pair DATA LANE IN_1+ IN_1− AC-coupled differential pair DATA LANE IN_2+ IN_2− AC-coupled differential pair IN_3+ DATA LANE IN_3− X+ X− AUX DATA OUT+ OUT− CBTL06121 D0+ D0− TX0+ TX0− D1+ D1− TX1+ TX1− D2+ D2− TX2+ TX2− D3+ D3− TX3+ TX3− HPD RX1+ X− to RX1− path matches X+ to RX1+ path SPARE RX1− AUX+ AUX− RX0+ RX0− PEG CONNECTOR OR DOCKING CONNECTOR 002aad092 Rev. 01 — 23 May 2008 © NXP B.V. 2008. All rights reserved. 5 of 19 5 Page NXP Semiconductors CBTL06121 www.DataSheet4U.com Gen1 hex display multiplexer 10. Characteristics 10.1 General characteristics Table 8. Symbol IDD Ptot tstartup trcfg General characteristics Parameter Conditions supply current operating mode (XSD = HIGH); VDD = 3.3 V shutdown mode (XSD = LOW); VDD = 3.3 V total power consumption operating mode (XSD = HIGH); VDD = 3.3 V start-up time supply voltage valid or XSD going HIGH to channel speciﬁed operating characteristics reconﬁguration time SEL state change to channel speciﬁed operating characteristics Min - - - - - Typ 0.2 - - - - 10.2 DisplayPort channel characteristics Table 9. DisplayPort channel characteristics Symbol Parameter Conditions VI VIC VID DDIL input voltage common-mode input voltage differential input voltage differential insertion loss channel is on; 0 Hz ≤ f ≤ 1.0 GHz channel is on; f = 2.5 GHz channel is off; 0 Hz ≤ f ≤ 3.0 GHz DDRL differential return loss channel is on; 0 Hz ≤ f ≤ 1.0 GHz DDNEXT differential near-end crosstalk adjacent channels are on; 0 Hz ≤ f ≤ 1.0 GHz B bandwidth −3.0 dB intercept tPD propagation delay from left-side port to right-side port or vice versa tsk(dif) tsk differential skew time skew time intra-pair inter-pair Min Typ −0.3 - 0- −1.2 - −2.5 −1.6 −4.5 - -- -- -- - 25 - 180 -- -- 10.3 AUX and DDC ports Table 10. Symbol VI VIC VID tPD AUX and DDC port characteristics Parameter Conditions input voltage DDC or AUX common-mode input voltage DDC or AUX differential input voltage propagation delay from left-side port to right-side port or vice versa Min −0.3 0 −1.2 [1] - Typ - - - 180 [1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time. Max 1 10 5 1 1 Max +2.6 2.0 +1.2 - - −20 −10 −30 - - 5 180 Max +2.6 2.0 +1.2 - Unit mA µA mW ms ms Unit V V V dB dB dB dB dB GHz ps ps ps Unit V V V ps CBTL06121_1 Product data sheet Rev. 01 — 23 May 2008 © NXP B.V. 2008. All rights reserved. 11 of 19 11 Page

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