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Número de pieza IDT72P51549
Descripción 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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1.8V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION
589,824 bits
1,179,648 bits
2,359,296 bits
4,718,592 bits
ADVANCE INFORMATION
www.DIDaTta7S2hPe5e1t54U3.9com
IDT72P51549
IDT72P51559
IDT72P51569
FEATURES
Choose from among the following memory density options:
IDT72P51539 Total Available Memory = 589,824 bits
IDT72P51549 Total Available Memory = 1,179,648 bits
IDT72P51559 Total Available Memory = 2,359,296 bits
IDT72P51569 Total Available Memory = 4,718,592 bits
Configurable from 1 to 32 Queues
Default configuration of 32 or 16 symmetrical queues
Default multi-queue device configurations
– IDT72P51539: 512 x 36 x 32Q
– IDT72P51549: 1,024 x 36 x 32Q
– IDT72P51559: 2,048 x 36 x 32Q
– IDT72P51569: 4,096 x 36 x 32Q
Default configuration can be augmented via the queue address
bus
Number of queues and individual queue sizes may be
configured at master reset though serial programming
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Independent Read and Write access per queue
User Selectable Bus Matching Options:
– x36 in to x36 out – x18 in to x36 out
– x9 in to x36 out
– x36in to x18out
– x18 in to x18 out
– x9 in to x18 out
– x36in to x9out
– x18 in to x9 out
– x9 in to x9 out
User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL
100% Bus Utilization, Read and Write on every clock cycle
Selectable First Word Fall Through (FWFT) or IDT standard
mode of operation
Ability to operate on packet or word boundaries
Mark and Re-Write operation
Mark and Re-Read operation
Individual, Active queue flags (OR / EF, IR / FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Direct or polled operation of flag status bus
Expansion of up to 256 queues and/or 32Mb logical configura-
tion using up to 8 multi-queue devices in parallel
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
WRADD
WEN 8
WCLK
WCS
Din
x36, 18 or x9
DATA IN
FF/IR
PAF
PAFn
8
Q31
Q30
Q29
Q0
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RADEN
ESTR
RDADD
8 REN
RCLK
RCS
OE
Qout
x36, x18 or x9
DATA OUT
EF/OR
PR
PAE
PAEn
8 PRn
6715 drw01
SEPTEMBER 2004
DSC-6715/-

1 page




IDT72P51549 pdf
IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DESCRIPTION
The IDT72P51539/72P51549/72P51559/72P51569 multi-queue flow-con-
trol devices are single chips with up to 32 discrete configurable FIFO queues.
All queues within the device have a common data input bus, (write port) and
a common data output bus, (read port). Data written into the write port is directed
to a specific queue via an internal de-multiplex operation, addressed by the write
address bus (WRADD). Data read from the read port is accessed from a specific
queue via an internal multiplex operation, addressed by the read address bus
(RDADD). Data writes and reads can be performed at high speeds up to
200MHz, with access times of 3.6ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and a
different queue on the read port or both ports may select the same queue
simultaneously.
The device provides Full flag and Empty flag status for the queue selected
for write and read operations respectively. Also a Programmable Almost Full
and Programmable Almost Empty flag for each queue is provided. Two 8 bit
programmable flag busses are available, providing status of queues not
selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when more
than 8 queues are used, either a Polled or Direct mode bus operation provides
the flag busses with all queues status.
Bus Matching is available on this device, either port can be 9 bits, 18 bits or
36 bits wide. When Bus Matching is used the device ensures the logical transfer
of data throughput in a Little Endian manner.
A packet mode of operation is also provided. Packet mode provides a packet
ready flag output (PR) indicating when at least one (or more) packets of data
within a queue is available for reading. The Packet Ready indicator is generated
upon detection of the start and end of packet demarcatiwonwbwits.D. TahteamShuletie-qtu4eUu.ce om
device then provides the user with an internally generated packet ready status
per queue.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
A Master Reset must be provided to the device. A Master Reset latches in
configuration/setup pins and must be performed before further programming of
the device can take place. On the rising edge of master reset the device operating
mode is set, the device programming mode (serial, parallel or default) is set and
the expansion configuration device type (master or slave) is set.
The multi-queue flow-control device has the capability of operating its I/O in
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of I/O is selected
via the IOSEL input. The core supply voltage (VDD) to the multi-queue is 1.8V,
however the output levels can be set independently via a separate supply,
VDDQ.
A JTAG test port is provided, here the multi-queue flow-control device has
a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an
outline of the functional blocks within the device.
5 SEPTEMBER 27, 2004

5 Page





IDT72P51549 arduino
IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
FF/IR
(P8)
Name
Full Flag/
Input Ready
I/O TYPE
Description
www.DataSheet4U.com
HSTL-LVTTL
OUTPUT
This pin provides the full flag output for the active Queue, that is, the queue selected on the input port
for write operations, (selected via WCLK, WRADD bus and WADEN). On the 3rd WCLK cycle after a queue
selection, this flag will show the status of the newly selected queue. Data can be written to this queue on
the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during
expansionofdevices,whentheFF flagoutputofupto8devicesmaybeconnectedtogetheronacommon
line. The device with a queue selected takes control of the FFbus, all other devices place their FFoutput
into High-Impedance. When a queue selection is made on the write port this output will switch from
High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.
FM(1)
(K16)
Flag Mode
HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the
INPUT FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled
or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
FSTR
(R4)
PAFn Flag Bus
Strobe
HSTL-LVTTL
INPUT
If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK
and the WRADD bus to select a status word of queues to be placed on to thePAFn bus outputs. A status
word addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH.
If Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus
selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
FSYNC
(R3)
PAFn Bus Sync HSTL-LVTTL
OUTPUT
FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus
during Polled operation of thePAFn bus. During Polled operation each status word of queue status flags
is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads
status word 1 on to PAFn, the second WCLK rising edge loads status word 2 and so on. The fifth WCLK
rising edge will again load status word 1. During the WCLK cycle that status word 1 of a selected device
is placed on to the PAFn bus, the FSYNC output will be HIGH. For all other status words of that device,
the FSYNC output will be LOW.
FWFT
(R11)
First Word Fall HSTL-LVTTL First word fall through (FWFT) or IDT Standard mode is selected during a Master Reset cycle. To select
Through
INPUT FWFTmodeasserttheFWFTsignal=LOW,ifFWFT=HIGHduringthemasterresetthenIDTStandard
mode is selected.
FXI
PAFn Bus
HSTL-LVTTL The FXI input is used when multi-queue devices are connected in expansion configuration and Polled
(T2)
Expansion In
INPUT PAFn bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The
FXI receives a token from the previous device in a chain. In single device mode the FXI input must be
tied LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI
input must be connected to the FXO output of the same device. In expansion configuration the FXI of the
first device should be tied LOW, when direct mode is selected.
FXO
PAFn Bus
HSTL-LVTTL FXO is an output that is used when multi-queue devices are connected in expansion configuration and
(T3) ExpansionOut OUTPUT Polled PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.
This pin pulses when device N has placed its final (4th) status word on to the PAFn bus with respect to
WCLK. This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK
rising edge the first status word of device N+1 will be loaded on to the PAFn bus. This continues through
the chain and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of
each device in the chain provides synchronization to the user of this looping event.
ID[2:0](1)
(ID2-C9
ID1-A10
ID0-B10)
Device ID Pins
HSTL-LVTTL
INPUT
For the 32Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue
selection takes place the 1-3 MSb’s of this 8 bit address bus are used to address the specific device (the
5-7 LSb’s are used to address the queue within that device). During write/read operations the 1-3 MSb’s
of the address are compared to the device ID pins. In an eight device expansion configuration, the first
device in a chain of multi-queue’s (connected in expansion configuration), may be setup as ‘000' (this is
referred to as the Master Device), the second as ‘001’ and so on through to device 8 which is ‘111’, however
the ID does not have to match the device order. In single device mode these pins should be setup as ‘000’
and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The ID[2:0] inputs
setup a respective devices ID during master reset. These ID pins must not toggle during any device
operation. Note, the device selected as the ‘Master’ must be ID ‘000’. In serial programming, the master
device (ID 000) must be programmed last.
11 SEPTEMBER 27, 2004

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