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PDF LH28F800BJHE-PTTLT6 Data sheet ( Hoja de datos )

Número de pieza LH28F800BJHE-PTTLT6
Descripción Flash Memory 8Mbit (512Kbitx16 / 1Mbitx8)
Fabricantes Sharp Microelectronics 
Logotipo Sharp Microelectronics Logotipo



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No Preview Available ! LH28F800BJHE-PTTLT6 Hoja de datos, Descripción, Manual

PRODUCT SPECIFICATION
Integrated Circwuwiwts.DaGtarSoheuept4U.com
LH28F800BJHE-PTTLT6
Flash Memory
8Mbit (512Kbitx16 / 1Mbitx8)
(Model Number: LHF80JT6)
Spec. Issue Date: October 26, 2004
Spec No: EL16192

1 page




LH28F800BJHE-PTTLT6 pdf
LHF80JT6
2
LH28F800BJHE-PTTLT6
8M-BIT ( 512Kbit ×16 / 1Mbit ×8 )
Boot Block Flash MEMORY
www.DataSheet4U.com
Low Voltage Operation
VCC=VCCW=2.7V-3.6V Single Voltage
OTP(One Time Program) Block
3963 word + 4 word Program only array
User-Configurable ×8 or ×16 Operation
High-Performance Read Access Time
90ns(VCC=2.7V-3.6V)
Operating Temperature
-40°C to +85°C
Low Power Management
Typ. 2µA (VCC=3.0V) Standby Current
Automatic Power Savings Mode Decreases ICCR in
Static Mode
Typ. 120µA (VCC=3.0V, TA=+25°C, f=32kHz)
Read Current
Optimized Array Blocking Architecture
Two 4K-word (8K-byte) Boot Blocks
Six 4K-word (8K-byte) Parameter Blocks
Fifteen 32K-word (64K-byte) Main Blocks
Top Boot Location
Extended Cycling Capability
Minimum 100,000 Block Erase Cycles
Enhanced Automated Suspend Options
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
Enhanced Data Protection Features
Absolute Protection with VCCWVCCWLK
Block Erase, Full Chip Erase, Word/Byte Write and
Lock-Bit Configuration Lockout during Power
Transitions
Block Locking with Command and WP#
Permanent Locking
Automated Block Erase, Full Chip Erase,
Word/Byte Write and Lock-Bit Configuration
Command User Interface (CUI)
Status Register (SR)
SRAM-Compatible Write Interface
Industry-Standard Packaging
48-Lead TSOP
ETOXTM* Nonvolatile Flash Technology
CMOS Process (P-type silicon substrate)
Not designed or rated as radiation hardened
The product is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications.
The product can operate at VCC=2.7V-3.6V and VCCW=2.7V-3.6V or 11.7V-12.3V. Its low voltage operation capability
realize battery life and suits for cellular phone application.
Its Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component
suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code
+ data storage applications.
For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to
DRAM, the product offers four levels of protection: absolute protection with VCCWVCCWLK, selective hardware block
locking or flexible software block locking. These alternatives give designers ultimate control of their code security needs.
The product is manufactured on SHARP’s 0.25µm ETOXTM* process technology. It come in industry-standard package: the
48-lead TSOP, ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 1.27

5 Page





LH28F800BJHE-PTTLT6 arduino
LHF80JT6
8
2.1 Data Protection
When VCCWVCCWLK, memory contents cannot be
altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
even when high voltage is applied to VCCW. All write
functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The device’s
block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and word/byte write operations.
Refer to Table 5 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the VCCW voltage. RP#
can be at VIH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from reset mode, the device automatically
resets to read array mode. Six control pins dictate the data
flow in and out of the component: CE#, OE#, BYTE#,
WE#, RP# and WP#. CE# and OE# must be driven active
to obtain data at the outputs. CE# is the device selection
control, and when active enables the selected memory
device. OE# is the data output (DQ0-DQ15) control and
when active drives the selected memory data onto the I/O
bus. BYTE# is the device I/O interface mode control.
WE# must be at VIH, RP# must be at VIH, and BYTE#
and WP# must be at VIL or VIH. Figure 16, 17 illustrates
read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device outputs
are disabled. Output pins (DQ0-DQ15) are placed in a
high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) placews wtwhe.DadteavSihceeeitn4U.com
standby mode which substantially reduces device power
consumption. DQ0-DQ15 outputs are placed in a high-
impedance state independent of OE#. If deselected during
block erase, full chip erase, word/byte write or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation completes.
3.4 Reset
RP# at VIL initiates the reset mode.
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100ns. Time tPHQV is required after return from reset
mode until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase, full chip erase, word/byte write or
lock-bit configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset operation
is complete. Memory contents being altered are no longer
valid; the data may be partially erased or written. Time
tPHWL is required after RP# goes to logic-high (VIH)
before another command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase, full chip erase, word/byte write or
lock-bit configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization may not
occur because the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal
that resets the system CPU.
Rev. 1.27

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