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Número de pieza | LH28F008SCHT-TE | |
Descripción | Flash Memory 8M (1Mb x 8) | |
Fabricantes | Sharp Microelectronics | |
Logotipo | ||
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No Preview Available ! PRELIMINARY PRODUCT SPECIFICATION
Integrated Circwuwiwts.DaGtarSoheuept4U.com
LH28F008SCHT-TE
Flash Memory
8M (1Mb x 8)
(Model Number: LHF08CTE)
Lead-free (Pb-free)
Spec. Issue Date: October 6, 2004
Spec No: EL16X024
1 page LHF08CTE
2
LH28F008SCHT-TE
8M-BIT (1MB x 8)
SmartVoltage Flash MEMORY
www.DataSheet4U.com
■ SmartVoltage Technology
2.7V(Read-Only), 3.3V or 5V VCC
3.3V, 5V or 12V VPP
■ High-Performance Read Access Time
85ns(5V±0.25V), 90ns(5V±0.5V),
120ns(3.3V±0.3V), 150ns(2.7V-3.6V)
■ Operating Temperature
-40°C to +85°C
■ High-Density Symmetrically-Blocked
Architecture
Sixteen 64K-byte Erasable Blocks
■ Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
■ Enhanced Data Protection Features
Absolute Protection with VPP=GND
Flexible Block Locking
Block Erase/Byte Write Lockout
during Power Transitions
■ Automated Byte Write and Block Erase
Command User Interface
Status Register
■ Enhanced Automated Suspend Options
Byte Write Suspend to Read
Block Erase Suspend to Byte Write
Block Erase Suspend to Read
■ Extended Cycling Capability
100,000 Block Erase Cycles
1.6 Million Block Erase Cycles/Chip
■ SRAM-Compatible Write Interface
■ Industry-Standard Packaging
40-Lead TSOP
■ ETOXTM* Nonvolatile Flash Technology
■ CMOS Process
(P-type silicon substrate)
■ Not designed or rated as radiation
hardened
SHARP’s LH28F008SCHT-TE Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F008SCHT-TE offers three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
The LH28F008SCHT-TE is manufactured on SHARP’s 0.38µm ETOXTM process technology. It come in
industry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA
architecture, the LH28F008SCHT-TE enables quick and easy upgrades for designs demanding the state-of-the-art.
*ETOX is a trademark of Intel Corporation.
Rev. 1.3
5 Page LHF08CTE
8
3 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from deep power-down mode,
the device automatically resets to read array mode.
Four control pins dictate the data flow in and out of
the component: CE#, OE#, WE#, and RP#. CE# and
OE# must be driven active to obtain data at the
outputs. CE# is the device selection control, and
when active enables the selected memory device.
OE# is the data output (DQ0-DQ7) control and when
active drives the selected memory data onto the I/O
bus. WE# must be at VIH and RP# must be at VIH or
VHH. Figure 15 illustrates a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ7 are
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ7 outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
consuming active power untwil wwt.hDeataSohpeert4aUti.ocnom
completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, byte write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP#
goes to logic-high (VIH) before another command can
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array
data. SHARP’s flash memories allow proper CPU
initialization following a system reset through the use
of the RP# input. In this application, RP# is controlled
by the same RESET# signal that resets the system
CPU.
Rev. 1.3
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet LH28F008SCHT-TE.PDF ] |
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