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PDF LH28F320S3HNS-ZM Data sheet ( Hoja de datos )
| Número de pieza | LH28F320S3HNS-ZM | |
| Descripción | Flash Memory 32Mbit (4Mbitx8/2Mbitx16) | |
| Fabricantes | Sharp Microelectronics | |
| Logotipo |  |
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PRELIMINARY PRODUCT SPECIFICATION
Integrated Circwuwiwts.DaGtarSoheuept4U.com
LH28F320S3HNS-ZM
Flash Memory
32Mbit (4Mbitx8/2Mbitx16)
(Model Number: LHF32KZM)
Lead-free (Pb-free)
Spec. Issue Date: October 15, 2004
Spec No: EL16X116
1 page  
LHF32KZM
2
LH28F320S3HNS-ZM
32M-BIT (4MBx8/2MBx16)
Smart 3 Flash MEMORY
www.DataSheet4U.com
■ Smart 3 Technology
2.7V or 3.3V VCC
2.7V, 3.3V or 5V VPP
■ Common Flash Interface (CFI)
Universal & Upgradable Interface
■ Scalable Command Set (SCS)
■ High Speed Write Performance
32 Bytes x 2 plane Page Buffer
2.7 µs/Byte Write Transfer Rate
■ High Speed Read Performance
110ns(3.3V±0.3V), 140ns(2.7V-3.6V)
■ Operating Temperature
-40°C to +85°C
■ High-Density Symmetrically-Blocked
Architecture
Sixty-four 64K-byte Erasable Blocks
■ Extended Cycling Capability
100,000 Block Erase Cycles
6.4 Million Block Erase Cycles/Chip
■ Enhanced Automated Suspend Options
Write Suspend to Read
Block Erase Suspend to Write
Block Erase Suspend to Read
■ Automated Write and Erase
Command User Interface
Status Register
■ Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
■ Enhanced Data Protection Features
Absolute Protection with VPP=GND
Flexible Block Locking
Erase/Write Lockout during Power
Transitions
■ SRAM-Compatible Write Interface
■ User-Configurable x8 or x16 Operation
■ Industry-Standard Packaging
56-Lead SSOP
■ ETOXTM* V Nonvolatile Flash
Technology
■ CMOS Process
(P-type silicon substrate)
■ Not designed or rated as radiation
hardened
SHARP’s LH28F320S3HNS-ZM Flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F320S3HNS-ZM offers three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
The LH28F320S3HNS-ZM is conformed to the flash Scalable Command Set (SCS) and the Common Flash
Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device
data transfer rates and minimize device and system-level implementation costs.
The LH28F320S3HNS-ZM is manufactured on SHARP’s 0.4µm ETOXTM* V process technology. It come in
industry-standard package: the 56-Lead SSOP, ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 1.6
5 Page 
LHF32KZM
8
3 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, query structure, or status register independent
of the VPP voltage. RP# must be at VIH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, Query
or Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-down
mode, the device automatically resets to read array
mode. Five control pins dictate the data flow in and
out of the component: CE# (CE0#, CE1#), OE#, WE#,
RP# and WP#. CE0#, CE1# and OE# must be driven
active to obtain data at the outputs. CE0#, CE1# is
the device selection control, and when active enables
the selected memory device. OE# is the data output
(DQ0-DQ15) control and when active drives the
selected memory data onto the I/O bus. WE# and
RP# must be at VIH. Figure 17, 18 illustrates a read
cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ15 are
placed in a high-impedance state.
3.3 Standby
Either CE0# or CE1# at a logic-high level (VIH) places
the device in standby mode which substantially
reduces device power consumption. DQ0-DQ15
outputs are placed in a high-impedance state
independent of OE#. If deselected during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, the device continues
functioning, and consuming activwewwp.oDwaetarShuenettil4Ut.hceom
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP#
goes to logic-high (VIH) before another command can
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.
Rev. 1.6
11 Page | ||
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