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PDF LH28F160S3HNS-TR Data sheet ( Hoja de datos )
| Número de pieza | LH28F160S3HNS-TR | |
| Descripción | Flash Memory 16M (2Mb x 8 / 1Mb x 16) | |
| Fabricantes | Sharp Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LH28F160S3HNS-TR (archivo pdf) en la parte inferior de esta página. Total 69 Páginas | ||
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PRODUCT SPECIFICATION
Integrated Circwuwiwts.DaGtarSoheuept4U.com
LH28F160S3HNS-TR
Flash Memory
16M (2Mb x 8 / 1Mb x 16)
(Model Number: LHF16KTR)
Spec. Issue Date: November 1, 2004
Spec No: EL16Y005
1 page  
LHF16KTR
2
LH28F160S3HNS-TR
16M-BIT (2MBx8/1MBx16)
Smart 3 Flash MEMORY
www.DataSheet4U.com
■ Smart 3 Technology
2.7V or 3.3V VCC
2.7V, 3.3V or 5V VPP
■ Common Flash Interface (CFI)
Universal & Upgradable Interface
■ Scalable Command Set (SCS)
■ High Speed Write Performance
32 Bytes x 2 plane Page Buffer
2.7 µs/Byte Write Transfer Rate
■ High Speed Read Performance
100ns(3.3V±0.3V), 120ns(2.7V-3.6V)
■ Operating Temperature
-40°C to +85°C
■ Enhanced Automated Suspend Options
Write Suspend to Read
Block Erase Suspend to Write
Block Erase Suspend to Read
■ High-Density Symmetrically-Blocked
Architecture
Thirty-two 64K-byte Erasable Blocks
■ SRAM-Compatible Write Interface
■ User-Configurable x8 or x16 Operation
■ Enhanced Data Protection Features
Absolute Protection with VPP=GND
Flexible Block Locking
Erase/Write Lockout during Power
Transitions
■ Extended Cycling Capability
100,000 Block Erase Cycles
3.2 Million Block Erase Cycles/Chip
■ Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
■ Automated Write and Erase
Command User Interface
Status Register
■ Industry-Standard Packaging
56-Lead SSOP
■ ETOXTM* V Nonvolatile Flash
Technology
■ CMOS Process
(P-type silicon substrate)
■ Not designed or rated as radiation
hardened
SHARP’s LH28F160S3HNS-TR Flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S3HNS-TR offers three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
The LH28F160S3HNS-TR is conformed to the flash Scalable Command Set (SCS) and the Common Flash
Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device
data transfer rates and minimize device and system-level implementation costs.
The LH28F160S3HNS-TR is manufactured on SHARP’s 0.35µm ETOXTM* V process technology. It come in
industry-standard package: the 56-Lead SSOP ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 2.0
5 Page 
LHF16KTR
8
3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code, device code, block status codes
for each block (see Figure 4). Using the manufacturer
and device codes, the system CPU can automatically
match the device with its proper algorithms. The
block status codes identify locked or unlocked block
setting and erase completed or erase uncompleted
condition.
1FFFFF
1F0006
1F0005
1F0004
1F0003
1F0000
1EFFFF
020000
01FFFF
010006
010005
010004
010003
010000
00FFFF
Reserved for
Future Implementation
Block 31 Status Code
Reserved for
Future Implementation
Block 31
(Blocks 2 through 30)
Reserved for
Future Implementation
Block 1 Status Code
Reserved for
Future Implementation
Block 1
Reserved for
Future Implementation
000006
000005
000004
000003
000002
000001
000000
Block 0 Status Code
Device Code
Manufacturer Code Block 0
Figure 4. Device Identifier Code Memory Map
3.6 Query Operation
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The query operation outputs the query structure.
Query database is stored in the 48Byte ROM. Query
structure allows system software to gain critical
information for controlling the flash component.
Query structure are always presented on the lowest-
order data output (DQ0-DQ7) only.
3.7 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
VCC=VCC1/2 and VPP=VPPH1/2/3, the CUI additionally
controls block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Word/byte Write command requires the
command and address of the location to be written.
Set Block Lock-Bit command requires the command
and block address within the device (Block Lock) to
be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 19 and 20 illustrate
WE# and CE#-controlled write operations.
4 COMMAND DEFINITIONS
When the VPP voltage ≤ VPPLK, Read operations from
the status register, identifier codes, query, or blocks
are enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
Rev. 2.0
11 Page | ||
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| PDF Descargar | [ Datasheet LH28F160S3HNS-TR.PDF ] | |
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