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PDF M29W008DB Data sheet ( Hoja de datos )

Número de pieza M29W008DB
Descripción 8 Mbit 3V Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M29W008DT
M29W008DB
8 Mbit (1Mb x 8, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
SUPPLY VOLTAGE
– 2.7V to 3.6V for Program, Erase and Read
ACCESS TIMES: 70ns, 90ns
PROGRAMMING TIME: 10µs per Byte typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Embedded Byte Program Algorithm
– Status Register bits and Ready/Busy
Output
19 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom location)
– 2 Parameter and 16 Main Blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTIPLE BLOCK PROTECTION/
TEMPORARY UNPROTECTION MODE
ERASE SUSPEND and RESUME MODES
LOW POWER CONSUMPTION
– Standby and Automatic Standby modes
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– M29W008DT Device Code: D2h
– M29W008DB Device Code: DCh
Figure 1. Package
TSOP40 (N)
10 x 20mm
August 2004
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M29W008DB pdf
M29W008DT, M2w9wWw0.D0a8taDShBeet4U.com
SUMMARY DESCRIPTION
The M29W008D is a 8 Mbit (1Mb x 8) non-volatile
Flash memory that can be read, erased at block,
multi-block or chip level and programmed at Byte
level. These operations are performed using a sin-
gle 2.7V to 3.6V VCC supply voltage. For Program
and Erase operations the necessary high voltages
are generated internally. The device can also be
programmed using standard programming equip-
ment.
The memory is divided into blocks that are asym-
metrically arranged. Both M29W008DT and
M29W008DB devices have an array of 19 blocks
composed of one Boot Block of 16 KBytes, two
Parameter Blocks of 8 KBytes, one Main Block of
32 KBytes and fifteen Main Blocks of 64 KBytes. In
the M29W008DT, the Boot Block is located at the
top of the memory address space while in the
M29W008DB, it is located at the bottom. The
memory maps are showed in Figure 4., Block Ad-
dresses (Top Boot Block) and Figure 5., Block Ad-
dresses (Bottom Boot Block). Each block can be
erased and reprogrammed independently so it is
possible to preserve valid data while old data is
erased. Program and Erase commands are written
to the Command Interface of the memory. An on-
chip Program/Erase Controller simplifies the pro-
cess of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. Erase opera-
tions in one block can be temporarily suspended in
order to read from or program in blocks that are
not being erased. Each block can be programmed
and erased over 100,000 cycles.
Each block can be protected independently to pre-
vent accidental Program or Erase commands from
modifying the memory. All previously protected
blocks can be temporarily unprotected.
The device is offered in TSOP40 (10 x 20mm)
package and supplied with all the bits erased (set
to ’1’).
Table 1. Signal Names
A0-A19
Address Inputs
DQ0-DQ7 Data Input/Outputs, Command Inputs
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
Figure 2. Logic diagram
VCC
20
A0-A19
15
DQ0-DQ7
W
M29W008DT
E M29W00DB
G RB
RP
VSS
AI08169
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M29W008DB arduino
M29W008DT, M2w9wWw0.D0a8taDShBeet4U.com
Table 2. Bus Operations
Operation
E G W RP
Byte Read
VIL VIL VIH VIH
Byte Write
VIL VIH VIL VIH
Output Disable
Standby
VIL VIH VIH VIH
VIH X
X VIH
Read
Manufacturer Code
VIL VIL VIH VIH
Electronic
signature
Device
M29W008DT
Code M29W008DB
VIL
VIL
VIH
VIH
Note: 1. X = VIL or VIH.
Address Inputs A0-A19
Cell Address
Command Address
X
X
A0= VIL, A1= VIL, A9=VID,
others address bits are ‘Don’t Care’
A0= VIH, A1= VIL, A9=VID,
others address bits are ‘Don’t Care’
DQ0-
DQ7
Data
Output
Data
Input
Hi-Z
Hi-Z
20h
D2h
DCh
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