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PDF ZGP323L Data sheet ( Hoja de datos )
| Número de pieza | ZGP323L | |
| Descripción | general-purpose microcontroller | |
| Fabricantes | Zilog | |
| Logotipo |  |
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Z8 GPTM Microcontrollers
ZGP323L OTP MCU Family
Preliminary Product Specification
PS023702-1004
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
1 page  
Z8 GPTM OTP MCU Family
Product Specification
www.DataSheet4U.com
v
Figure 35. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 36. Stop Mode Recovery Register 2 ((0F)DH:D2–D4, D6 Write Only) . 59
Figure 37. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . 60
Figure 38. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 39. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted) 64
Figure 40. T8 and T16 Common Control Functions ((0D)01H: Read/Write) . . . 65
Figure 41. T16 Control Register ((0D) 2H: Read/Write Except Where Noted) . 67
Figure 42. T8/T16 Control Register (0D)03H: Read/Write
(Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 43. Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 44. Port Configuration Register (PCON)(0F)00H: Write Only) . . . . . . . 70
Figure 45. Stop Mode Recovery Register ((0F)0BH: D6–D0=Write Only,
D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 46. Stop Mode Recovery Register 2 ((0F)0DH:D2–D4, D6 Write Only) 72
Figure 47. Watch-Dog Timer Register ((0F) 0FH: Write Only) . . . . . . . . . . . . . 73
Figure 48. Port 2 Mode Register (F6H: Write Only) . . . . . . . . . . . . . . . . . . . . . 73
Figure 49. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . 74
Figure 50. Port 0 and 1 Mode Register (F8H: Write Only) . . . . . . . . . . . . . . . . 75
Figure 51. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . 76
Figure 52. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . 77
Figure 53. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . 77
Figure 54. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 55. Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 56. Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . 79
Figure 57. Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 58. 20-Pin CDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 59. 20-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 60. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 61. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 62. 28-Pin CDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 63. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 64. 28-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 65. 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 66. 40-Pin CDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 67. 40-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 68. 48-Pin SSOP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
PS023702-1004
Preliminary
5 Page 
Z8 GPTM OTP MCU Family
Product Specification
www.DataSheet4U.com
5
P25
P26
P27
P07
VDD
XTAL2
XTAL1
P31
P32
P33
1
2
3
4
5
6
7
8
9
10
20-Pin
PDIP
SOIC
SSOP
CDIP*
20 P24
19 P23
18 P22
17 P21
16 P20
15 VSS
14 P01
13 P00/Pref1/P30
12 P36
11 P34
Figure 3. 20-Pin PDIP/SOIC/SSOP/CDIP* Pin Configuration
Table 3. 20-Pin PDIP/SOIC/SSOP/CDIP* Pin Identification
Pin #
1–3
4
5
6
7
8–10
11,12
13
14
15
16–20
Symbol
Function
Direction
P25–P27
Port 2, Bits 5,6,7
Input/Output
P07 Port 0, Bit 7
Input/Output
VDD
XTAL2
Power Supply
Crystal Oscillator Clock
Output
XTAL1
Crystal Oscillator Clock
Input
P31–P33
Port 3, Bits 1,2,3
Input
P34. P36
Port 3, Bits 4,6
Output
P00/Pref1/P30 Port 0, Bit 0/Analog reference input Input/Output for P00
Port 3 Bit 0
Input for Pref1/P30
P01 Port 0, Bit 1
Input/Output
VSS
P20–P24
Ground
Port 2, Bits 0,1,2,3,4
Input/Output
Note: *Windowed Cerdip. These units are intended to be used for
engineering code development only. ZiLOG does not
recommend/guarantee this package for production use.
PS023702-1004
Preliminary
Pin Description
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZGP323L.PDF ] | |
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