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PDF K7D161874B Data sheet ( Hoja de datos )

Número de pieza K7D161874B
Descripción 512Kx36 & 1Mx18 SRAM
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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K7D163674B
K7D161874B
512Kx36 & 1Mx1w8wwS.DRatAaShMeet4U.com
Document Title
16M DDR SYNCHRONOUS SRAM
Revision History
Rev No.
History
Rev. 0.0
Initial document.
Rev. 0.1
Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS
-to support 1.8~2.5V VDD, change some items.
Rev. 0.2
Change DC CHARACTERISTICS (Stop Clock Standby Current)
-ISB1 : 100 -> 150
Rev. 0.3
Change JTAG Instruction Cording
- For Reserved
Rev. 1.0
Change DC CHARACTERISTICS (Increase Operating Current)
- x36 : add 40mA, x18 : add 60mA
Rev. 1.1
Add DC CHARACTERISTICS
- VIN-CLK, VDIF-CLK, VCM-CLK
Add AC INPUT CHARACTERISTICS
Add INPUT DEFINITION
Draft Data
Oct. 2003
Nov. 2003
Feb. 2004
Feb. 2004
Mar. 2004
Jan. 2004
Remark
Advance
Preliminary
Preliminary
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
Rev 1.1
Jan. 2005

1 page




K7D161874B pdf
K7D163674B
K7D161874B
512Kx36 & 1Mx1w8wwS.DRatAaShMeet4U.com
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least one NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and
are equal to RQ/5. For example, 250resistor will give an output impedance of 50. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates
occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In
all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior
in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is
selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-
uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are
no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs
1024 non-read cycles.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
-5-
Rev 1.1
Jan. 2005

5 Page





K7D161874B arduino
K7D163674B
K7D161874B
512Kx36 & 1Mx1w8wwS.DRatAaShMeet4U.com
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
NOP
READ
READ
READ CONTINUE READ
CONTINUE READ
NOP
(burst of 4)
(burst of 4)
(burst of 2)
NOP
WRITE
READ
WRITE CONTINUE READ
CONTINUE
(burst of 4)
(burst of 4)
1 2 3 4 5 6 7 8 9 10 11 12
K
tKHKH
tKHKL
tKLKH
K
B1
B2
tBVKH
B3
tKHBX
SA A0
tAVKH
tKHAX
G
DQ QX2
A5 A1
A2 A3
tGHQX
tGHQZ
Q01 Q02 Q03 Q04 Q51 Q52 Q53 Q54 Q11 Q12
tKHDX
tDVKH
D21 D22
tGLQV
tGLQX
D23 D24
Q31
tCHQZ
CQ
CQ
tKXCV tCHQV
tCHLZ
tCHQX tCLQV
tKXCL
tCHCL tCLCH
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
- 11
Rev 1.1
Jan. 2005

11 Page







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