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PDF K4Y54084UF Data sheet ( Hoja de datos )

Número de pieza K4Y54084UF
Descripción XDR/RDRAM
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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K4Y5416(/08/04)4UF
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XDR DRAM
256Mbit XDR DRAM(F-die)
2M x 16(/8/4) bit x 8s Banks
Version 1.0
Jan. 2005
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Version 1.0 Jan. 2005

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K4Y54084UF pdf
K4Y5416(/08/04)4UF
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XDR DRAM
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for
normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N”
appended to a signal name denotes the complementary signal of a differential pair.
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of
a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit-windows
on each signal, while the DQ bus uses a set of 16 bit-windows on each signal.
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) com-
mand. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A second
request packet at clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to
column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T3 contains another write (WR) command.
This causes the data packet D(a2) at edge T6 to also be written to column Ca2. A final request packet at clock edge T13 contains
a precharge (PRE) command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-W , tCC , and
tWRP . In addition, the spacing between the request packets and data packets is constrained by the tCWD parameter. The spacing
of the CFM/CFMN clock edges is constrained by tCYCLE.
Figure 1 : XDR DRAM Device Write and Read Transactions
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT WR
a0 a1
WR
a2
DQ15..0tRCD-W
DQN15..0
tCC
tCWD
D(a1)
tWRP
D(a2)
PRE
a3
tCYCLE
Transaction a: WR a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
CFM
CFMN
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0 ACT
a0
DQ15..0
DQN15..0
tRCD-R
RD
a1
tCC
RD
a2 tRDP
tCAC
PRE
a3
Q(a1)
Q(a2)
tCYCLE
Transaction a: RD a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of
the memory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a
read (RD) command. This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for
bank Ba. A third request packet at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13
to also be read from column Ca2. A final request packet at clock edge T10 contains a PRE command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-R , tCC , and
tRDP . In addition, the spacing between the request and data packets are constrained by the tCAC parameter.
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K4Y54084UF arduino
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XDR DRAM
Figure 3 : Request Packet Formats
CCFFMM
CCFFMMNN
RQ11..0
RQ11..0
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE ACT
a0
RD
WRM
PRE
PDN
a1 a2 a3
-
DQ15..0
DQN15..0
ROWA Packet
tCYCLE
CFM
CFMN
RQ11
RQ10
RQ9
RQ8
RQ7
RQ6
RQ5
RQ4
RQ3
RQ2
RQ1
RQ0
OP DEL
3A
OP R
28
RR
97
RR
10 6
rsrv R
5
rsrv R
4
rsrv R
3
rsrv R
2
rsrv R
1
BA R
20
BA rsrv
1
BA rsrv
0
COL Packet
tCYCLE
OP DEL
3C
OP rsrv
2
OP rsrv
1
OP rsrv
0
WR C
X7
CC
86
CC
95
rsrv C
4
rsrv SC
3
BC SC
22
BC SC
11
BC SC
00
COLM Packet
tCYCLE
ROWP Packet
tCYCLE
COLX Packet
tCYCLE
OP M
37
MM
36
MM
25
MM
14
MC
07
CC
86
CC
95
rsrv C
4
rsrv SC
3
BC SC
22
BC SC
11
BC SC
00
OP POP
32
OP ROP
22
OP ROP
11
OP ROP
00
POP RA
17
POP RA
06
rsrv RA
5
rsrv RA
4
rsrv RA
3
BP RA
22
BP RA
11
BP RA
00
OP rsrv
3
OP rsrv
2
OP rsrv
1
OP rsrv
0
rsrv rsrv
rsrv rsrv
rsrv rsrv
rsrv rsrv
XOP rsrv
3
XOP rsrv
2
XOP rsrv
1
XOP rsrv
0
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