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PDF SC68C652B Data sheet ( Hoja de datos )
| Número de pieza | SC68C652B | |
| Descripción | 5 Mbit/s (max.) with 32-byte FIFOs | |
| Fabricantes | NXP Semiconductors | |
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SC68C652B
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte
FIFOs, IrDA encoder/decoder, and Motorola µP interface
Rev. 01 — 25 April 2005
Product data sheet
1. General description
The SC68C652B is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
The SC68C652B is pin compatible with the SC68C2550B. The SC68C652B provides
enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode data
transfer, and infrared (IrDA) encoder/decoder. The DMA mode data transfer is controlled
by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers
provide the user with error indications and operational status. System interrupts and
modem control features may be tailored by software to meet specific user requirements.
An internal loop-back capability allows on-board diagnostics. Independent programmable
baud rate generators are provided to select transmit and receive baud rates.
The SC68C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in the plastic LQFP48 package.
2. Features
s 2 channel UART with Motorola® µP interface
s 5 V, 3.3 V and 2.5 V operation
s 5 V tolerant inputs
s Industrial temperature range (−40 °C to +85 °C)
s Software compatible with industry standard 16C450, 16C550, and SC16C650
s Up to 5 Mbit/s baud rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
s 32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
s Independent transmit and receive UART control
s Four selectable receive and transmit FIFO interrupt trigger levels
s Automatic software (Xon/Xoff) and hardware (RTS/CTS) flow control
s Programmable Xon/Xoff characters
s Software selectable baud rate generator
s Standard modem interface or infrared IrDA encoder/decoder interface
s Supports IrDA version 1.0 (up to 115.2 kbit/s)
s Sleep mode
s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
s Transmit, Receive, Line Status, and Data Set interrupts independently controlled
1 page  
Philips Semiconductors
SC68C652B
www.DataSheet4U.com
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Table 2: Pin description …continued
Symbol
Pin Type Description
D0 to D7
44, 45,
46, 47,
48, 1, 2,
3
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
DSRA, DSRB 39, 20 I
Data Set Ready (active LOW). These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is
powered-on and is ready for data exchange with the UART. These pins have no effect
on the UART’s transmit or receive operation.
DTRA, DTRB 34, 35 O
Data Terminal Ready (active LOW). These outputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC68C652B
is powered-on and ready. These pins can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the
modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or
after a reset. These pins have no effect on the UART’s transmit or receive operation.
GND
17, 24 I
Signal and power ground
IRQ 30 O Interrupt Request. Interrupts from UART channels A-B are wire-ORed internally to
function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the
interrupt enable register) whenever a UART channel(s) requires service. Individual
channel interrupt status can be determined by addressing each channel through its
associated internal register, using CS and A3. An external pull-up resistor must be
connected between this pin and VCC.
R/W 15 I A logic LOW on this pin will transfer the contents of the data bus (D[0:7]) from an
external CPU to an internal register that is defined by address bits A[0:2]. A logic HIGH
on this pin will load the contents of an internal register defined by address bits A[0:2] on
the SC68C652B data bus (D[0:7]) for access by an external CPU.
n.c.
12, 25, -
not connected
29, 37
OP2A, OP2B 32, 9 O
Output 2 (user-defined). This function is associated with individual channels A and B.
The state of these pins is defined by the user through the software settings of MCR[3].
OP2A/OP2B is a logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1 when
MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.
RESET
36 I Reset (active LOW). This pin will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during reset time. See
Section 7.11 “SC68C652B external reset condition” for initialization details.
RIA, RIB
41, 21 I
Ring Indicator (active LOW). These inputs are associated with individual UART
channels A and B. A logic 0 on these pins indicates the modem has received a ringing
signal from the telephone line. A logic 1 transition on these input pins generates an
interrupt.
RTSA, RTSB 33, 22 O
Request to Send (active LOW). These outputs are associated with individual UART
channels, A and B. A logic 0 on the RTS pin indicates the transmitter has data ready
and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this
pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1.
These pins have no effect on the UART’s transmit or receive operation.
RXA, RXB 5, 4 I
Receive data input. These inputs are associated with individual serial channel data to
the SC68C652B receive input circuits A and B. The RX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled. During the local loop-back
mode, these RX input pins are disabled and TX data is connected to the UART RX input
internally.
RXRDYA,
RXRDYB
31, 18 O
Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the trigger level
has been reached or the FIFO has at least one character. It goes HIGH when the RX
FIFO is empty.
9397 750 14657
Product data sheet
Rev. 01 — 25 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 41
5 Page 
Philips Semiconductors
SC68C652B
www.DataSheet4U.com
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.8 Programmable baud rate generator
The SC68C652B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC68C652B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is capable
of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is
necessary to use full rail swing on the clock input. The SC68C652B can be configured for
internal or external clock operation. For internal clock oscillator operation, an industry
standard microprocessor crystal is connected externally between the XTAL1 and XTAL2
pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see Table 6).
The generator divides the input 16× clock by any divisor from 1 to (216 − 1). The
SC68C652B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in Table 6 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
XTAL1
XTAL2
X1
1.8432 MHz
Fig 3. Crystal oscillator connection
C1
22 pF
C2
33 pF
002aab325
9397 750 14657
Product data sheet
Rev. 01 — 25 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 41
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