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PDF SDN0080G Data sheet ( Hoja de datos )
| Número de pieza | SDN0080G | |
| Descripción | 80-Segment Dot-matrix STN LCD Driver | |
| Fabricantes | Avant Electronics | |
| Logotipo |  |
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DATA SHEET
www.DataSheet4U.com
SDN0080G
80-Segment Dot-matrix
STN LCD Driver
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
data sheet (v3)
2005 Oct 03
1 page  
Avant Electronics
SDN0080G
80-Segment Dot-matrix STN LCD Driver
3.2 Signal description
Table 2 Pin signal description.
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To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
Pin
number
SYMBOL
I/O
DESCRIPTION
1~80 O1~O80
Segment driver output.
Output Please refer to Table 3 for output voltage level.
81 CDI
82, 83,
84
V1, V3, V4
Input
Input
Chip Disable pin.
When CDI=High, on-chip data reception circuit is disabled and data can not be
sent into the SDN0080G.
When CDI=LOW, data can be sent into the SDN0080G.
LCD bias voltage.
V1 and VEE are selected levels.
V3 and V4 are unselected levels.
85 VEE
86 M
87 LOAD
88 VSS
89 DISPOFF
90
91
92, 93,
94
VDD
R/L
NC
95, 96,
97, 98
DI4 ~ DI1
99 CP
100 CDO
Input
Input
Input
Input
Input
Input
Input
Negative power supply for LCD bias.
Frame signal.
Display data (80 bits) latch clock. At the falling edge of the LOAD signal, 80-bit
segment data is transferred from the first latch to the second latch for output. (
Refer to Fig. 1, Functional Block Diagram.
Ground.
Display Disable.
When DISPOFF=L, the outputs O1~O81 are all at a fixed level of V1.
Power supply for control logic.
Shift direction control for display data reception from a controller.
No Connection.
These pins are not used in application and must be left open.
4-bit parallel data bus for interfacing with a controller.
Input
The 4 bits of data are latched into the SDN0080G at the falling edge of the CP
clock.
Please refer to Fig 3.
Display data latch clock.
Input
4 bits of display data (DI1~DI4) are latched into the internal 80-bit latch at the
falling edge of CP.
Please refer to Fig 3.
Output Cascading output when the SDN0080G are used in cascade.
2005 Oct 03
5 of 18
data sheet (v3)
5 Page 
Avant Electronics
SDN0080G
80-Segment Dot-matrix STN LCD Driver
9 TIMING CHART ( 1/240 DUTY, 1/16 BIAS)
9.1 1/240 duty timing chart
240 1
2
240 1
2
240 1
2
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LOAD
01~O80
M
M
LOAD
DI1~DI4
CP
D1~D80
9.2 1/16 bias
240 1
2
LOAD
Latch Data
M
LH
L
VDD (V1)
Va
Vb (V3)
O1 ~O80
Vc (V4)
Vd
Ve (VEE)
240 1
2
LHL
Fig.6 1/240 duty timing chart
240 1
2
L HL
VDD
V1 VDD
Va
Vb
VLCD
Vc
Vd
Ve
R
R
12R
R
R
V3
V4
VEE
VR
VSS
Refer to Fig. 8 for
VEE enlarged view.
Va = VDD - (1/16) VLCD
Vb = VDD - (2/16) VLCD
VLCD
Vc = VDD - (14/16) VLCD
Vd = VDD - (15/16) VLCD
Ve = VDD - (16/16) VLCD
Fig.7 1/16 bias
2005 Oct 03
11 of 18
data sheet (v3)
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SDN0080G.PDF ] | |
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