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PDF SCN0080G_A Data sheet ( Hoja de datos )
| Número de pieza | SCN0080G_A | |
| Descripción | 80-Segment Dot-matrix STN LCD Driver | |
| Fabricantes | Avant Electronics | |
| Logotipo |  |
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DATA SHEET
www.DataSheet4U.com
SCN0080G_A,
SCN0080G_B
80-Segment Dot-matrix
STN LCD Driver
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
data sheet (v3)
2005 Oct 05
1 page  
Avant Electronics
SCN0080G_A, SCN0080G_B
80-Segment Dot-matrix STN LCD Driver
3.2 Signal description
Table 2 Pin signal description.
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To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
Pin number
SCN0080G_ SCN0080G_
AB
SYMBOL
I/O
DESCRIPTION
1~80
80~1
O1~O80
Segment driver output.
Output Please refer to Table 3 for output voltage level.
99
92, 89, 88
82
89, 92, 93
CDI Input
V1, V3, V4 Input
Chip Disable pin.
When CDI=High, on-chip data reception circuit is disabled and
data can not be sent into the SCN0080G_A, SCN0080G_B.
When CDI=LOW, data can be sent into the SCN0080G_A,
SCN0080G_B.
LCD bias voltage.
V1 and VEE are selected levels.
V3 and V4 are unselected levels.
87
93
98
86
84
91
85
81, 83, 90
94
88
83
95
97
90
96
91, 98, 100
VEE
M
LOAD
VSS
DISPOFF
VDD
P/S
NC
Input
Input
Input
Input
Input
Input
Input
Negative power supply for LCD bias.
Frame signal, for generating alternating LCD bias voltages.
Display data (80 bits) latch clock. At the falling edge of the LOAD
signal, 80-bit segment data is transferred from the first latch to
the second latch for output. ( Refer to Fig. 1, Functional Block
Diagram.
Ground.
Display Disable.
When DISPOFF=L, the outputs O1~O81 are all at a fixed level of
V1.
Power supply for control logic.
Selection of parallel or serial interface with a controller.
When P/S= HIGH, 4-bit parallel interface is selected.
When P/S=LOW, serial interface is selected.
No Connection.
These pins are not used in application and must be left open.
2005 Oct 05
5 of 22
data sheet (v3)
5 Page 
Avant Electronics
8 OUTPUT TIMING DIAGRAM
1 23
CP
SCN0080G_A, SCN0080G_B
80-Segment Dot-matrix STN LCD Driver
one scan line ( n x 80 pixels )
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19 20 21
DI1
DI4
LOAD
CDO(No.1)
CDO(No.2)
CDO(No.3)
CDO(No.n)
O1~O80
IC number 1 data acquisition period
IC number 2 data
acquisition period
IC number 3 data
acquisition period
IC number n data
acquisition period
Fig.6 Output timing diagram
2005 Oct 05
11 of 22
data sheet (v3)
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet SCN0080G_A.PDF ] | |
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