|
|
PDF K1B3216BDD Data sheet ( Hoja de datos )
| Número de pieza | K1B3216BDD | |
| Descripción | 2Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory | |
| Fabricantes | SAMSUNG ELECTRONICS | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de K1B3216BDD (archivo pdf) en la parte inferior de esta página. Total 42 Páginas | ||
|
No Preview Available !
K1B3216BDD
UtRAMwww.DataSheet4U.com
Document Title
2Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
Revision History
Revision No. History
0.0 Initial Draft
- Design target
Draft Date
Remark
September 02, 2004 Preliminary
0.1 Revised
November 01, 2004 Preliminary
- Corrected the name of 9th row of balls on the pakage to ’J’ from ’I’
on page.2 and page.42
1.0 Finalize
April 06, 2005
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 1.0
April 2005
1 page  
K1B3216BDD
LIST of FIGURES
Figure 1. Pin Description
Figure 2. Functional Block Diagram
Figure 3. Power Up Timing
Figure 4. Standby Mode State Machine
Figure 5. Mode Register Setting Timing
Figure 6. Asynchronous 4-Page Read
Figure 7. Asynchronous Write
Figure 8. Synchronous Burst Read
Figure 9. Synchronous Burst Write
Figure 10. Latency Configuration(Read)
Figure 11. WAIT Control and Read/Write Latency Control
Figure 12. AC Output Load Circuit(Asynchronous)
Figure 13. Timing Waveform of Asynchronous Read Cycle
Figure 14. Timing Waveform of Page Read Cycle
Figure 15. Timing Waveform of Write Cycle(Asynchronous, WE Controlled)
Figure 16. Timing Waveform of Write Cycle(Asynchronous, UB & LB Controlled)
Figure 17. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, WE Controlled)
Figure 18. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, UB & LB Controlled)
Figure 19. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, WE Controlled)
Figure 20. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, UB & LB Controlled)
Figure 21. Timing Waveform of Multiple Write Cycle(Asynchronous, Low ADV Type, WE Controlled )
Figure 22. AC Output Load Circuit(Synchronous)
Figure 23. Timing Waveform of Basic Burst Operation
Figure 24. Timing Waveform of Burst Read Cycle(CS Toggling Consecutive Burst Read)
Figure 25. Timing Waveform of Burst Read Cycle(CS Low Holding Consecutive Burst Read)
Figure 26. Timing Waveform of Burst Read Cycle(Last Data Sustaining)
Figure 27. Timing Waveform of Burst Write Cycle(CS Toggling Consecutive Burst Write)
Figure 28. Timing Waveform of Burst Write Cycle(CS Low Holding Consecutive Burst Write)
Figure 29. Timing Waveform of Burst Read Stop by CS
Figure 30. Timing Waveform of Burst Write Stop by CS
Figure 31. Timing Waveform of Burst Read Suspend Cycle
Figure 32. Synch. Burst Read to Asynch. Write(Address Latch Type) Timing Waveform
Figure 33. Synch. Burst Read to Asynch. Write(Low ADV Type) Timing Waveform
Figure 34. Asynch. Write(Address Latch Type) to Synch. Burst Read Timing Waveform
Figure 35. Asynch. Write(Low ADV Type) to Synch. Burst Read Timing Waveform
Figure 36. Synch. Burst Read to Synch. Burst Write Timing Waveform
Figure 37. Synch. Burst Write to Synch. Burst Read Timing Waveform
UtRAMwww.DataSheet4U.com
Page
2
6
7
7
11
12
12
12
12
13
14
16
17
28
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
- 5 - Revision 1.0
April 2005
5 Page 
K1B3216BDD
UtRAMwww.DataSheet4U.com
MODE REGISTER SETTING TIMING
This device supports software access control type mode register setting timing. This timing consists of 5 cycles of Read operation.
Each cycle of Read Operation is normal asynchronous read operation. Clock and ADV are don’t care and WAIT signal is High-Z. CS
should be toggling between cycles. The address for 1st, 2nd and 3rd cycle should be 1FFFFF(h) and the address for 4th cycle should
be 1FFEFF. The address for 5th cycle should be MRS code(Register setting values).
MRS TIMING WAVEFORM(Clock, ADV, UB, LB are Don’t care, WAIT=High-Z)
Address
CS
OE
1FFFFF
tRCM
1FFFFF
tCHM tCLM
1FFFFF
1FFEFF
MRS CODE
WE
AC CHARACTERISTICS
Parameter
Read Cycle time
CS High pulse width
Sym-
tRCM
tCHM
Min Max Unit
Parameter
70 - ns CS Low pulse width
10 - ns
Sym-
tCLM
Mi Ma
60 -
Unit
ns
- 11 -
Revision 1.0
April 2005
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet K1B3216BDD.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| K1B3216BDD | 2M x 16 bit Synchronous Burst Uni-Transistor CMOS RAM |  Samsung Semiconductor |
| K1B3216BDD | 2Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory | SAMSUNG ELECTRONICS |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |