|
|
PDF LF3324 Data sheet ( Hoja de datos )
| Número de pieza | LF3324 | |
| Descripción | 24Mbit Frame Buffer/FIFO | |
| Fabricantes | LOGIC DEVICES | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LF3324 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
|
No Preview Available !
DEVICES INCORPORATED
LF3324
24Mbit Frame Buffer / FIFO
Prelimiwnwawry.DaDtaaSthaeseth4Ue.ecotm
Features
24,883,200-bit Frame Memory
74.25 Mhz Data Rate
May be Organized Into the Following Configurations:
• 3,110,400 x 8-bit
• 2,488,320 x 10-bit
• 2,073,600 x 12-bit
Operating Modes:
• Random Access with Burst Control
• FIFO
• Synchronous Shift Register
Near-Full/Empty Flags With Programmable
Thresholds
Flexible Pointer Manipulation
• Write and Read Pointers may be independently
jumped to arbitrary address locations
• Write or Read Pointers can be manipulated in real-
time based on external 24bit address
LF3324s may be Cascaded for depth and
width, supporting HDTV, Multiframe SDTV,
and other high resolution formats
• Seamless address space is maintained
with up to 8 cascaded devices
Built-in ITU-R BT.656 TRS detection and
Synchronization
Set & Clear Read/Write Pointer Control Pins
Choice of Control Interfaces:
• Two-wire Serial Microprocessor Interface
• Parallel Microprocessor Interface
Input Enable Control (Write Mask) for freeze-
frame applications
Output Enable Control (Data Skipping)
JTAG Boundary Scan - IEEE 1149.1
172 ball LBGA package
1.8V Internal Core Power Supply
3.3V I/O Supply
NOTE: This Preliminary Datasheet references LF3324BGC Engineering Samples
with an E marking under the part designation.
Applications
DTV/HDTV Video Stream Buffer
Frame Synchronization
CCTV Security Camera Systems
Time Base Correction (TBC)
Freeze-Frame Buffer
Regional Read/Write for Picture-in-Picture (PIP)
Field-Based or Frame-Based Comb Filtering
Video Capture & Editing Systems
Deep Data Buffering
Video Special Effects (Rotation, Zoom)
Test Pattern Generation
Motion Detection or Frame-to-Frame Correlation
LOGIC Devices Incorporated
Video Imaging Product
September 14, 2005 LDS.3324 E
1 page  
DEVICES INCORPORATED
LF3324
24Mbit Frame Buffer / FIFO
Prelimiwnwawry.DaDtaaSthaeseth4Ue.ecotm
Operating Modes
through setting (jumping) the write pointer to the 24bit address via the ADDR[23:0] port or to the WADDR
configuration register. Read pointer manipulation can be done through setting (jumping) the write pointer
to the 24bit address via the ADDR[23:0] port or to the RADDR configuration register. Periodic write and
read pointer jumping can be accomplished by supplying an address through either the ADDR[23:0] external
address or the WADDR/RADDR instruction registers. Continuous random access can only be accomplished
through the use of the ADDR[23:0] ports. When the write/read pointers are not being set to an address,
they increment sequentially in burst mode.
In Random Access Mode, when WADRSEL = 1 and RADRSEL = 0 the write pointer is set to the address
supplied by the ADDR[23:0] ports when WSET is brought LOW. In other words, on each active write clock
cycle (rising edge of WCLK for which WEN was LOW two rising edges of WCLK previously), the user
directs the write pointer to any desired memory location, using what are otherwise the second channel
data input and output ports. In this application, ADDR[23:12] denotes the vertical (row) component,
and ADDR[11:0], the horizontal (column) component, of a Cartesian set. Setting the configuration
register ROW_LENGTH to the frame’s line (row) length internally defines the Cartesian coordinates. Also,
ADDR[23:0] can also represent a single 24-bit linear address. The user governs the mapping of (ADDR)
to the internal memory space by setting the parameter ROW_LENGTH such that the internal ADDRESS
= ADDR[23-12] * ROW_LENGTH + ADDR[11-0]. A ROW_LENGTH setting of 0 is interpreted as 4096,
such that ADDRESS = a 24-bit concatenation of {ADDR} for this particular value. For a standard D1 video
application with 1716 samples per line, the user would set ROW_LENGTH to 1716 decimal = 6B4 hex.
Offset circuitry within the LF3324 permits the user to cascade several chips in parallel and to use them
collectively as a single large memory with a seamless address space. Data are read out sequentially by
rising edges of RCLK, under the control of REN (read enable), RSET (read pointer force to constant), and
RCLR (read pointer clear to 0). Holding WSET LOW keeps the device continuously in random access
write mode. Releasing WSET to its HIGH state causes the chip to continue to write sequentially from
the last-loaded address.
In Random Access Mode, when RADRSEL = 1, WADRSEL = 0, MARK_SEL = 1, the read pointer is set
to the address supplied by the ADDR[23:0] ports when RSET is brought LOW. As mentioned above,
ADDR[23:12] represents the upper bits or the vertical (row) address, whereas ADDR[11:0] represents the
lower bits or the horizontal (column) address. Releasing RSET HIGH causes the read address pointer to
increment from its last assigned location to the next sequential address.
It is important to note that WSET and RSET can be programmed to be level or negative-edge triggered.
An edge sensitive “SET” command is useful for using SYNC signals to reset FIFO pointers. Level sensitive
“SET” commands allow full-time Random Access capability.
LOGIC Devices Incorporated
Video Imaging Product
5 September 14, 2005 LDS.3324 E
5 Page 
DEVICES INCORPORATED
LF3324
24Mbit Frame Buffer / FIFO
Prelimiwnwawry.DaDtaaSthaeseth4Ue.ecotm
Detailed Signal Definitions
is active, holding this pin LOW will hold the write address in its zero position continuously. This control
takes effect only when WEN is LOW.
RADDRSEL - Read Address Select
RADDRSEL selects the source of the read address. This pin and control MARKSEL select whether
RSET forces the read address to the RADDR configuration register (RADDRSEL = 0) or to ADDR[23:0]
(RADDRSEL = 1). This control takes effect only when REN is LOW.
WSET - Write Pointer Set
This control is active only when WCLR is HIGH. Bringing WSET LOW will cause the next rising edge
of WCLK to bring the current value on D[11:0] into memory at the address specified by WADDR, or at
the address present on ADDR[23:0]. Whenever WSET and WCLR are HIGH, the next rising edge of
WCLK will bring the current D[11:0] data value into the next-higher address in sequence. WSET may be
programmed to be either edge-triggered, in which case it affects the write pointer for only one clock cycle
following a falling edge, after which incrementing resumes, or level-triggered, in which case it affects the
write pointer until it is brought HIGH. For continuous random access write operation, holding WSET LOW
and programming it to be level-triggered will provide the needed continuous write pointer override. This
control takes effect only when WEN is LOW.
WADDRSEL - Write Pointer Set
WADDRSEL selects the source of the write address. WADDRSEL determines whether WSET forces
the write address pointer to the WADDR configuration register (WADDRSEL = 0) or to ADDR[23:0]
(WADDRSEL = 1). This control takes effect only when WEN is LOW.
MARK - Write Address Pointer Mark
Bringing this bit LOW will cause an internal register to store a copy the current value of the write address
pointer, for subsequent use in synchronizing the corresponding read address pointer to the same location.
Unlike WCLR and WSET, this control does not affect the write pointer value itself. The system must use
MARK instead of WCLR if the entire memory core can be filled between sequential falling edges of the
sync reference signal. In contrast, the system must use WCLR or WSET to establish a definite relationship
between the internal address and the data stream, as in random access read mode.
RSET - Read Address Pointer Set
If REN is LOW, bringing RSET LOW will force the read address to the most recently marked value
(MARK_SEL LOW), to RADDR (MARKSEL HIGH and RADRSEL LOW), or to ADDR[23:0] (MARK_SEL
is HIGH and RADRSEL is HIGH). This pin may be programmed to be either falling edge or level sensitive
active.
RCLR - Read Address Pointer Clear
Bringing RCLR LOW causes the next rising edge of RCLK to force the read address pointer to zero.
This pin may be programmed to be active on its falling edge or in its LOW state. It can reset the read
pointer only when REN is LOW.
WEN - Write Enable
If WEN is LOW, data on D11-0 is written to the device on the rising edge of WCLK. When WEN is HIGH,
the device ignores data on D and holds the write pointer. The user must anticipate the use of WEN by one
cycle. Therefore when desiring not to write a sample, WEN must be brought high the cycle before.
WIEN - Memory Write Enable (Write Masking)
WIEN is used to enable/disable writing into the memory core. A LOW on WIEN enables writing, while a
HIGH on WIEN disables writing. The internal write address pointer is incremented by WEN regardless of
the WIEN level. If disabling of WIEN is never desired, tie WIEN LOW.
LOGIC Devices Incorporated
Video Imaging Product
11 September 14, 2005 LDS.3324 E
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet LF3324.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LF3320 | Horizontal Digital Image Filter |  LOGIC Devices Incorporated |
| LF3321 | Horizontal Digital Image Filter |  LOGIC Devices |
| LF3324 | 24Mbit Frame Buffer/FIFO | LOGIC DEVICES |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |