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Número de pieza | ICS87974I | |
Descripción | LVCMOS/LVTTL CLOCK GENERATOR | |
Fabricantes | Integrated Circuit Systems | |
Logotipo | ||
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No Preview Available ! Integrated
Circuit
Systems, Inc.
ICS87974I
L S , 1- -15,OW KEwWww.DaTtaOSheet4U.com
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87974I is a low skew, low jitter 1-to-15
,&6 LVCMOS/LVTTL Clock Generator/Zero Delay
HiPerClockS™ Buffer and is a member of the HiPerClockS family
of high performance clock solutions from ICS. The
device has a fully integrated PLL and three banks
whose divider ratios can be independently controlled, providing
output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In ad-
dition, the external feedback connection provides for a wide
selection of output-to-input frequency ratios. The CLK0 and CLK1
pins allow for redundant clocking on the input and dynamically
switching the PLL between two clock sources. The ICS87974I
is pin for pin compatible with the MPC974.
Guaranteed low jitter and output skew characteristics make the
ICS87974I ideal for those applications demanding well defined
performance and repeatability.
FEATURES
• Fully integrated PLL
• 15 single ended 3.3V LVCMOS/LVTTL outputs
• 2 LVCMOS/LVTTL clock inputs for redundant clock applications
• CLK0 and CLK1 accepts the following input levels:
LVCMOS/LVTTL
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 500MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 350ps (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC974
PIN ASSIGNMENT
GND
nMR/OE
CLK_EN
SEL_B
SEL_C
PLL_SEL
SEL_A
CLK_SEL
CLK0
CLK1
nc
VDD
VDDA
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6 34
7
ICS87974I
33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
GND
QB1
VDDOB
QB2
GND
QB3
VDDOB
QB4
FB_IN
GND
QFB
VDDOFB
nc
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
87974AYI
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1
REV. B MAY 15, 2003
1 page Integrated
Circuit
Systems, Inc.
ICS87974I
L S , 1- -15,OW KEwWww.DaTtOaSheet4U.com
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
CIN
RPULLUP
RPULLDOWN
C
PD
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output); Note 1
V V , V = 3.465V
DD, DDA DDOx
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
15 pF
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
nMR/OE
CLK_EN
0X
10
11
QA0:QA4
HiZ
LOW
Enable
Outputs
QB0:QB4
QC0:QC3
HiZ HiZ
LOW
LOW
Enable
Enable
QFB
HiZ
Enable
Enable
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
TABLE 3C. PLL INPUT FUNCTION TABLE
CLK_SEL
0
1
Inputs
PLL Input
CLK0
CLK1
TABLE 3D. SELECT PIN FUNCTION TABLE
SEL_A
0
1
QAx
÷2
÷4
SEL_B
0
1
QBx
÷2
÷4
SEL_C
0
1
QCx
÷4
÷6
TABLE 3E. FB SELECT FUNCTION TABLE
Inputs
FB_SEL1
FB_SEL0
00
01
10
11
Outputs
QFB
÷4
÷6
÷8
÷ 12
TABLE 3F. VCO SELECT FUNCTION TABLE
VCO_SEL
0
1
Inputs
fVCO
VCO/2
VCO/4
87974AYI
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5
REV. B MAY 15, 2003
5 Page Integrated
Circuit
Systems, Inc.
ICS87974I
L S , 1- -15,OW KEwWww.DaTtOaSheet4U.com
LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
58.0°C/W
42.3°C/W
200
47.1°C/W
36.4°C/W
500
42.0°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87974I is: 4225
87974AYI
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REV. B MAY 15, 2003
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet ICS87974I.PDF ] |
Número de pieza | Descripción | Fabricantes |
ICS87974I | LVCMOS/LVTTL CLOCK GENERATOR | Integrated Circuit Systems |
ICS87974I | LVCMOS/LVTTL CLOCK GENERATOR | Integrated Device Technology |
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