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PDF SC28L201 Data sheet ( Hoja de datos )

Número de pieza SC28L201
Descripción high performance UART
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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SC28L201
www.DataSheet4U.com
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Rev. 01 — 31 October 2005
Product data sheet
1. General description
The SC28L201 is a high performance UART. Its functional and programming features
closely match but greatly extend those of previous Philips UARTs. Its configuration on
power-up is similar that of the SC26C92. Its differences from the previous Philips UARTs
are: 256-character receiver, 256-character transmit FIFOs, 3.3 V and 5 V compatibility,
8 I/O ports for arbitrating interrupt system and overall faster bus and data speeds and is
fabricated in an advanced 0.5 micron CMOS process.
It is a member of the IMPACT line of data communications parts.
Pin programming will allow the device to operate with either the Motorola or Intel bus
interface by changing the function of some pins (reset is inverted, DACKN, and IACKN
enabled, for example).
The Philips Semiconductors SC28L201 Universal Asynchronous Receiver/Transmitter
(UART) is a single-chip CMOS-LSI communications device that provides a full-duplex
asynchronous receiver/transmitter channel in a single package. It interfaces directly with
microprocessors and may be used in a polled or interrupt driven system. The use of the
Interrupt system provides intelligent interrupt vectors.
The operating mode and data format of the channel may be programmed independently.
Additionally, the receiver and transmitter can select its operating speed as one of
twenty-seven fixed baud rates; a 16× clock derived from one of two programmable
counter/timers, or an external 1× or 16× clock. The baud rate generator and counter/timer
can operate directly from a crystal or from external clock inputs. The ability to
independently program the operating speed of the receiver and transmitter make the
UART particularly attractive for dual-speed channel applications such as clustered
terminal systems and bridges.
Each receiver and transmitter is buffered by 256-character FIFOs to nearly eliminate the
potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in
interrupt driven systems. In addition, a flow control capability (Xon/Xoff and RTS/CTS) is
provided to disable a remote transmitter when the receiver buffer is full.
Also provided on the SC28L201 is a multipurpose 8-bit I/O for the channel. These can be
used as general-purpose I/O ports or can be assigned specific functions (such as clock
inputs or status and interrupt outputs) under program control. Normally they will be used
for modem control and DMA interface. All ports have change of state detectors and input
sections are always active making output signals available to the internal circuits and the
control processor.
The SC28L201 is available in a TSSOP48 package. For other package options, contact
Philips.

1 page




SC28L201 pdf
Philips Semiconductors
SC28L201
www.DataSheet4U.com
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
D0 to D7
SC28L201 (68000 mode)
8
BUS BUFFER
R/WN
IACKN
CEN
A0 to A6
RESETN
OPERATION
CONTROL
ADDRESS
DECODE
7
R/W CONTROL
IRQN
DACKN
INTERRUPT
ARBITRATION
IMR
ISR
GP
DATA CHANNEL
256-BYTE
TRANSMIT FIFO
TRANSMIT
SHIFT REGISTER
256-BYTE
RECEIVE FIFO
WATCHDOG
TIMER
RECEIVE
SHIFT REGISTER
MR0, 1, 2, 3
CR
SR
TXD
RXD
X1/SCLK
X2
SOFTWARE
FLOW CONTROL
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL
OSCILLATOR
CSR
ACR
CTL
CTU
I/O PORT A
CHANGE-OF-
STATE
DETECTORS (4)
IOPCR
ACR
8
I/O7A to I/O0A
I/O PORT B
FUNCTION
SELECT LOGIC
IOPCR
5
I/O0B
I/O4B to I/O2B
I/O6B
Fig 2. Block diagram of SC28L201 (68000 mode)
002aab570
9397 750 13138
Product data sheet
Rev. 01 — 31 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 110

5 Page





SC28L201 arduino
Philips Semiconductors
SC28L201
www.DataSheet4U.com
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
6.1.4 UART
The UART is a fully independent, full duplex and provides all normal asynchronous
functions: 5 to 8 data bits, parity odd or even, programmable stop bit length, false start bit
detection. Also provided are 256-byte FIFOs, Xon/Xoff software flow control, RTS/CTS
hardware flow control. The 9-bit mode address recognition with automatic RS485
turnaround. The BRG, Counter/Timer, or external clocks provide the baud rates. The
receivers and transmitters may operate in either the ‘1×’ or ‘16×’ modes.
The control section recognizes two address schemes. One is the subset of the other: a
four (4) bit and a seven (7) bit address spaces. The purpose of this is to provide a large
degree of software compatibility with previous Philips/Signetics UARTs.
6.1.5 Transmitter and receiver
The transmitter and receiver are independent devices capable of full duplex operation.
Baud rates, interrupt and status conditions are under separate control. Transmitter has
automatic simplex ‘turnaround’. Receiver has RTS and Xon/Xoff flow control and a
three-character recognition system.
6.1.6 Transmitter real time error check
This is a circuit used to verify that the correct data arrived at the destination. It is done real
time with one or two bit times of programmable delay. The purpose of this circuit is to
improve the response time of detecting problem data channels and to relieve the
processor burden and delay of checking data returned for validation.
The function is that the receiver returns the data received back to the transmitting station
where it is compared to a delayed version of the data sent. If an error occurs, and interrupt
may be generated for the particular bit that is in error. This is essentially a loopback
condition where circuits internal to the UART delay and compare the data returned.
It is suggested that a very high priority be set in the interrupt arbitration bidding control
register when the real time error detection is in use.
6.1.7 FIFO structures
The FIFO structure is 256 bytes for each of the two FIFOs in the UART. They are
organized as 11-bit words for the receiver and 8-byte words for the transmitter. The
interrupt level may be set at any value from 0 to 255. The interrupt level is independently
set for each FIFO.
FIFO interrupt and DMA fill/empty levels are controlled by the RXFIL and TXFIL registers
which may set any level of the from 0 to 255. The signals associated with the FIFO fill
levels are available to the I/O pins (for interrupt or DMA) and to the arbitrating interrupt
system for fine tuning of the arbitration authority.
6.1.8 Intelligent interrupt arbitration
The interrupt system uses a highly programmable arbitrating technique to establish when
an interrupt should be presented to the processor. The advantageous feature of this
system is the presentation of the context of the interrupt. It is presented in both a current
interrupt register and in the interrupt vector. The context of the interrupt shows the
interrupting channel, identifies which of the 11 possible sources in requesting interrupt
service and in the case of a receiver or transmitter gives the current fill level of the FIFO.
9397 750 13138
Product data sheet
Rev. 01 — 31 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 110

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