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PDF SAA7144HL Data sheet ( Hoja de datos )
| Número de pieza | SAA7144HL | |
| Descripción | Quadruple video input processor | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SAA7144HL
Quadruple video input processor
Rev. 01 — 21 April 2005
www.DataSheet4U.com
Product data sheet
1. General description
The SAA7144HL is a combination of four stand alone multistandard video decoders.
The SAA7144HL is a pure 3.3 V (5 V tolerant inputs and I/Os) CMOS circuit and a highly
integrated circuit for video surveillance applications. All four video decoders are based on
the principle of line-locked clock decoding and are able to decode the color of PAL,
SECAM and NTSC signals into “CCIR 601” compatible color component values.
The SAA7144HL accepts as analog inputs in total eight CVBS sources from TV or VTR
(two selectable CVBS sources for each of the four decoders).
Each of the four video decoders (A, B, C, D) contains an analog preprocessing circuit
including source selection for two CVBS sources, anti-aliasing filter and Analog-to-Digital
Converter (ADC), an automatic clamp and gain control, a Clock Generation Circuit (CGC),
a digital multistandard decoder (PAL, NTSC and SECAM), a Brightness Contrast
Saturation (BCS) control circuit, a multistandard text slicer see Figure 1 and a 27 MHz
VBI data bypass.
The integrated high performance multistandard data slicer supports several VBI data
standards:
• Teletext [WST (World Standard Teletext), CCST (Chinese teletext)] (625 lines)
• Teletext [US-WST, NABTS (North American Broadcast Text System) and MOJI
(Japanese teletext)] (525 lines)
• Closed caption [Europe, US (line 21)]
• Wide Screen Signalling (WSS)
• Video Programming Signal (VPS)
• Time codes (VITC EBU/SMPTE)
• HIGH-speed VBI data bypass for Intercast™ application.
The circuit is I2C-bus controlled via two I2C-bus interfaces where two video decoders
share one I2C-bus interface on different I2C-bus slave addresses. Each of the four video
decoders of the SAA7144HL uses a register mapping which is compatible to the
SAA7113H register mapping.
1 page  
Philips Semiconductors
7. Pinning information
7.1 Pinning
SAA7144HL
www.DataSheet4U.com
Quadruple video input processor
1 102
SAA7144HL
38 65
Fig 2. Pin configuration for LQFP128.
001aab305
7.2 Pin description
9397 750 14454
Product data sheet
Table 3: Pin description
Symbol
Pin
VSSA1(DECA)
1
VDDA1(DECA)
AI11_A
AI12_A
AI1D_A
2
3
4
5
AGND_A
DNC1
VDDA0(DECA)
VSSA0(DECA)
VSSA1(DECB)
VDDA1(DECB)
AI11_B
AI12_B
AI1D_B
6
7
8
9
10
11
12
13
14
AGND_B
DNC2
DNC3
VDDA0(DECB)
15
16
17
18
Description
analog ground for analog supply of the Analog-to-Digital Converter
(ADC) of video decoder A
analog supply voltage for the ADC (3.3 V) of video decoder A
analog input 11 of video decoder A
analog input 12 of video decoder A
differential analog input for AI11 and AI12 of video decoder A;
see Figure 28
analog ground reference for video decoder A
do not connect; leave open
analog supply voltage for the internal Clock Generation Circuit
(CGC) of video decoder A
analog ground for the internal CGC of video decoder A
analog ground for analog supply of the ADC of video decoder B
analog supply voltage for the ADC (3.3 V) of video decoder B
analog input 11 of video decoder B
analog input 12 of video decoder B
differential analog input for AI11 and AI12 of video decoder B;
see Figure 28
analog ground reference for video decoder B
do not connect; leave open
do not connect; leave open
analog supply voltage for the internal CGC of video decoder B
Rev. 01 — 21 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 64
5 Page 
Philips Semiconductors
SAA7144HL
www.DataSheet4U.com
Quadruple video input processor
ANALOG INPUT
AMPLIFIER
gain
DAC
9
ANTI-ALIAS FILTER
NO ACTION
ADC
8
1 VBLK 0
LUMA/CHROMA DECODER
1 HOLDG 0
1X0
0 > 254 1
1 HSY 0
0 <4 1
1 <1 0
1 > 254 0
1 > 248 0
X=0
+1/F
+1/L −1/LLC2
X=1
+1/LLC2 −1/LLC2
+/− 0
STOP
GAIN ACCUMULATOR (18 BITS)
ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]
1X0
1 HSY 0
1Y
AGV
UPDATE
0
FGV
GAIN VALUE 9-BIT
001aab307
X = system variable; Y = AGV – FGV > GUDL ; GUDL = gain update level (adjustable);
VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value;
FGV = frozen gain value.
Fig 7. Gain flow chart.
9397 750 14454
Product data sheet
Rev. 01 — 21 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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