DataSheet.es    


PDF ICS8633-01 Data sheet ( Hoja de datos )

Número de pieza ICS8633-01
Descripción 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



Hay una vista previa y un enlace de descarga de ICS8633-01 (archivo pdf) en la parte inferior de esta página.


Total 14 Páginas

No Preview Available ! ICS8633-01 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3wVwwLV.DaPtaEShCeeLt4U.com
ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS8633-01 is a high performance 1-to-3
ICS Differential-to-3.3V LVPECL Zero Delay Buffer
HiPerClockS™ and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
The ICS8633-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most standard
differential input levels. Utilizing one of the outputs as feed-
back to the PLL, output frequencies up to 700MHz can be
regenerated with zero delay with respect to the input. Dual
reference clock inputs support redundant clock or multiple
reference applications.
FEATURES
Three differential 3.3V LVPECL outputs
Selectable differential clock inputs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 25ps (maximum)
PLL reference zero delay: 50ps ± 100ps
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHs-compliant
packages
BLOCK DIAGRAM
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
0
1
÷4, ÷8
PLL
0
1
SEL0
SEL1
MR
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
PLL_SEL
VCC
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VCC
nFB_IN
FB_IN
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2 8 VCCA
27 VEE
26 VEE
2 5 VCCO
2 4 VCCO
23 Q2
22 nQ2
21 Q1
20 nQ1
19 Vcco
18 Vcco
17 Q0
16 nQ0
15 VEE
ICS8633-01
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm body package
F Package
Top View
8633AF-01
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 26, 2006

1 page




ICS8633-01 pdf
Integrated
Circuit
Systems, Inc.
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3wVwwL.VDaPtaEShCeeLt4U.com
ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC,
VCCA,
V
CCO
LVPECL
VEE
SCOPE
Qx
nQx
-1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
VCC
nCLK0,
nCLK1
CLK0,
CLK1
V
PP
Cross Points
VEE
DIFFERENTIAL INPUT LEVEL
V
CMR
nQx
Qx
nQy
Qy
t sk(o)
OUTPUT SKEW
80%
Clock 20%
Outputs
tR
OUTPUT RISE/FALL TIME
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ2
Q0:Q2
tPD
PROPAGATION DELAY
8633AF-01
nQ0:nQ2
Q0:Q2
tcycle n
tcycle n+1
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
80%
tF
VSW I N G
20%
CYCLE-TO-CYCLE JITTER
nQ0:nQ2
Q0:Q2
t PW
t
PERIOD
odc = t PW x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nCLK0,
nCLK1
CLK0,
CLK1
nFB_IN
FB_IN
t (Ø)
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
VOH
VOL
VOH
VOL
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER & STATIC PHASE OFFSET
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 26, 2006

5 Page





ICS8633-01 arduino
Integrated
Circuit
Systems, Inc.
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3wVwwL.VDaPtaEShCeeLt4U.com
ZERO DELAY BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
V
OUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
• For logic high, V = V = V
– 0.9V
OUT
OH_MAX
CCO_MAX
(V - V ) = 0.9V
CCO_MAX OH_MAX
• For logic low, V = V = V
– 1.7V
OUT
OL_MAX
CCO_MAX
(V - V ) = 1.7V
CCO_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OH_MAX
CCO_MAX
L CCO_MAX OH_MAX
CCO_MAX OH_MAX
L
CCO_MAX OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.2mW
Pd_L = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OL_MAX
CCO_MAX
L CCO_MAX OL_MAX
CCO_MAX OL_MAX
L
CCO_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8633AF-01
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 26, 2006

11 Page







PáginasTotal 14 Páginas
PDF Descargar[ Datasheet ICS8633-01.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS8633-011-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFERIntegrated Circuit Systems
Integrated Circuit Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar