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PDF K7P321888M Data sheet ( Hoja de datos )
| Número de pieza | K7P321888M | |
| Descripción | 1Mx36 & 2Mx18 SRAM | |
| Fabricantes | Samsung Electronics | |
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K7P323688M
K7P321888M
1Mx36 & 2Mx18wwSw.RDaAtaSMheet4U.com
32Mb M-die LW SRAM Specification
119BGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Dec. 2005
Rev 1.3
1 page  
K7P323688M
K7P321888M
1Mx36 & 2Mx18wwSw.RDaAtaSMheet4U.com
FUNCTION DESCRIPTION
The K7P323688M and K7P321888M are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of
36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.
Single differential HSTL level K clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising
edge of K clock, all Addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated
from output registers at the next rising edge of K clock. An internal write data buffer allows write data to follow one cycle after
addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is
read between first rising and falling edges of K clock. Data outputs are updated from output registers off the falling edge of K clock.
During consecutive read operations where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write Operation(Late Write)
During write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the
following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and
only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the
timing of SW[a:d] is the same as the SW signal.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array. Bypass read operation occurs on a byte to
byte basis. If only one byte is written during a write operation but a read operation is required on the same address, a partial bypass
read operation occurs since the new byte data is from the data in registers while the remaing bytes are from SRAM arry.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. Normal opera-
tions can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
Mode Control
There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDDQ. These
mode pins must be set at power-up and must not change during device operation.
Programmable Impedance Output Driver
The data output driver impedance is adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and is equal to RQ/5.
For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by test(10% by design)
and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that
do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance
updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Imped-
ance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and
proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles
have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up
requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-
read cycles. The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to VSS or VDDQ.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
-5-
Dec. 2005
Rev 1.3
5 Page 
K7P323688M
K7P321888M
1Mx36 & 2Mx18wwSw.RDaAtaSMheet4U.com
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left
unconnected.
JTAG Block Diagram
M1
TDI
TMS
TCK
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
M2
TDO
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0 0 0 SAMPLE-Z Boundary Scan Register 1
0 0 1 IDCODE Identification Register
2
0 1 0 SAMPLE-Z Boundary Scan Register 1
0 1 1 BYPASS Bypass Register
3
1 0 0 SAMPLE Boundary Scan Register 4
1 0 1 PRIVATE
5
1 1 0 BYPASS Bypass Register
3
1 1 1 BYPASS Bypass Register
3
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to VSS when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.
4. SAMPLE instruction does not places DQs in Hi-Z.
5. PRIVATE is reserved for the exclusive use of SAMSUNG. This
instruction should not be used.
TAP Controller State Diagram
1 Test Logic Reset
0
0 Run Test Idle
1
1
1
1
Select DR
0
Capture DR
0
Shift DR
1
Exit1 DR
0
Pause DR
1
Exit2 DR
1
Update DR
0
1
1
0
1
0
0
Select IR
0
Capture IR
0
Shift IR
1
Exit1 IR
0
Pause IR
1
Exit2 IR
1
Update IR
1
1
0
0
0
0
- 11
Dec. 2005
Rev 1.3
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet K7P321888M.PDF ] | |
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