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PDF ZL50411 Data sheet ( Hoja de datos )

Número de pieza ZL50411
Descripción Managed 9FE Layer-2 Ethernet Switch
Fabricantes Zarlink Semiconductor　
Logotipo Zarlink Semiconductor Logotipo



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No Preview Available ! ZL50411 Hoja de datos, Descripción, Manual

ZL50411
Managed 9FE Layer-2 Ethernet Switch
www.DataSheet4U.com
Data Sheet
Zarlink Features
• Integrated Single-Chip 10/100 Mbps Ethernet
Switch
• Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
• One 10/100 Mbps auto-negotiating port with
MII interface option, that can be used as a
WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port
with Reverse MII interface option
• Embedded 2.0 Mbits (256 KBytes) internal
memory for control databases and frame data
buffer
• Supports jumbo frames up to 4 KBytes
• CPU access supports the following interface
options:
• 8/16-bit ISA interface
• Serial interface with MII port; recommended
for light management
• Serial interface in lightly managed mode, or in
unmanaged mode with optional I2C EEPROM
interface
• Ethernet IEEE 802.3x flow control for full duplex
ports, back pressure flow control for half duplex
ports
April 2006
Ordering Information
ZL50411GDG 208-Ball LBGA
ZL50411GDG2 208-Ball LBGA**
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Built-in reset logic triggered by system
malfunction
• Built-In Self Test for internal SRAM
• IEEE-1149.1 (JTAG) test port
L2 Switching
• L2 switching
• MAC address self learning, up to 4 K MAC
addresses
• MAC address table supports unicast and
multicast MAC address and IP multicast
address learning
• Supports IP Multicast with IGMP snooping, up to
4 K IP Multicast groups
8/16-bit
or
C Serial
P
U
MII
I2C
EEPROM
ZL50411
9-Port 10/100M
Ethernet Switch
RMII / MII / GPSI
MII 10/100
PHY
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.

1 page




ZL50411 pdf
ZL50411
Data Sheet
January 2005
www.DataSheet4U.com
• Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable
June 2005
• Corrected ordering code to ZL50411GD”G”
• Clarified that port mirroring is only available if the source & destination ports are in RMII mode
• Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F
• Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap
TSTOUT[0]
• Added power sequencing recommendation (1.7, “Power Sequencing“ on page 25)
• Added Reverse MII/GPSI timing characteristics (13.4.10, “Reverse General Purpose Serial Interface
(RvGPSI)“ on page 139 and 13.4.11, “MII Management Data Interface (MDIO/MDC)“ on page 140)
• Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50411 (11.0, “Hardware Statistics
Counters“ on page 53)
December 2005
• Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3,
“Ball Signal Descriptions“ on page 14)
• Added more text to section 2.8, “JTAG“ on page 28
• Clarified counter definitions (11.0, “Hardware Statistics Counters“ on page 53)
• Added more explaination to VLAN ID Hashing feature: register FEN, bit [3]
• Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and
this bit was mistakenly left in the register definition.
April 2006
• Added Pb-free order code (ZL50411GDG2)
• Added section on multicast MAC address learning/switching (5.11, “L2 Multicast Switching“ on page 44)
since it wasn’t really discussed in the DS
• Clarified registers UCC, MCC & MCCTH
• Renamed register UCC (now PCC), as name was misleading
• Updated timing to CPU RvMII, as min. output delay should have been 0ns
5
Zarlink Semiconductor Inc.

5 Page





ZL50411 arduino
ZL50411
Data Sheet
Table of Contents
www.DataSheet4U.com
12.3.7.10 USD – One Micro Second Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.3.7.11 DEVICE - Device Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.3.7.12 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12.3.7.13 LHBTimer – Link Heart Beat Timeout Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.7.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.7.15 fMACCReg0, fMACCReg1 - MAC Control Frame OpCode . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.7.16 FCB Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.7.17 FCB Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.7.18 FCB Base Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3.8 (Group 7 Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3.8.1 MIRROR CONTROL – Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0~5 . . . . . . . . . . . . . . . . . 112
12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0~5 . . . . . . . . . . . . . . . . . . . . . 112
12.3.8.4 RMII_MIRROR0 – RMII Mirror 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.3.8.5 RMII_MIRROR1 – RMII Mirror 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.3.9 (Group 8 Address) Per Port QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.3.9.1 FCRn – Port 0~9 Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.3.9.2 BMRCn - Port 0~9 Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.3.9.3 PR100_n – Port 0~7 Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.9.4 PR100_CPU – Port CPU Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.9.5 PRM – Port MMAC Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.9.6 PTH100_n – Port 0~7 Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.9.7 PTH100_CPU – Port CPU Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.9.8 PTHG – Port MMAC Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.9.9 QOSC00, QOSC01 - Classes Byte Limit port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3.9.10 QOSC02, QOSC15 - Classes Byte Limit port 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3.9.11 QOSC16 - QOSC21 - Classes Byte Limit CPU port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3.9.12 QOSC22 - QOSC27 - Classes Byte Limit MMAC port . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3.9.13 QOSC28 - QOSC31 - Classes WFQ Credit For MMAC. . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.3.9.14 QOSC36 - QOSC39 - Shaper Control Port MMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.3.10 (Group E Address) System Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.3.10.1 DTSRL – Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.3.10.2 DTSRM – Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.3.10.3 TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.3.10.4 MASK0-MASK4 – Timeout Reset Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.3.10.5 BOOTSTRAP0 – BOOTSTRAP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.3.10.6 PRTFSMST0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.3.10.7 PRTQOSST0-PRTQOSST7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.3.10.8 PRTQOSST8A, PRTQOSST8B (CPU port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.3.10.9 PRTQOSST9A, PRTQOSST9B (MMAC port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.3.10.10 CLASSQOSST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.3.10.11 PRTINTCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.3.10.12 QMCTRL0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.3.10.13 QCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.3.10.14 BMBISTR0, BMBISTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.3.10.15 BMControl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.3.10.16 BUFF_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.3.10.19 FCB_NUM0, FCB_NUM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.3.10.20 BM_RLSFF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.3.10.21 BM_RSLFF_INFO[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11
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