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PDF UPD70F3707 Data sheet ( Hoja de datos )

Número de pieza UPD70F3707
Descripción 32-Bit Single-Chip Microcontrollers
Fabricantes NEC Electronics 
Logotipo NEC Electronics Logotipo



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No Preview Available ! UPD70F3707 Hoja de datos, Descripción, Manual

Preliminary User’s Manual
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V850ES/HG2
32-Bit Single-Chip Microcontrollers
Hardware
µPD70F3706
µPD70F3707
Document No. U17718EJ1V0UD00 (1st edition)
Date Published December 2005 N CP(K)
Printed in Japan
2005

1 page




UPD70F3707 pdf
PREFACE
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Readers
Purpose
Organization
This manual is intended for users who wish to understand the functions of the
V850ES/HG2 and design application systems using the V850ES/HG2.
This manual is intended to give users an understanding of the hardware functions of
the V850ES/HG2 shown in the Organization below.
This manual is divided into two parts: Hardware (this manual) and Architecture
(V850ES Architecture User’s Manual).
Hardware
Pin functions
CPU function
On-chip peripheral functions
Flash memory programming
Electrical specifications (target)
Architecture
Data types
Register set
Instruction format and instruction set
Interrupts and exceptions
Pipeline operation
How to Read This Manual
It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/HG2
Read this manual according to the CONTENTS.
To find the details of a register where the name is known
Use APPENDIX A REGISTER INDEX.
To understand the details of an instruction function
Refer to the V850ES Architecture User’s Manual available separately.
To know the electrical specifications of the V850ES/HG2
See CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET).
Register format
The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note
with caution that if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
Preliminary User’s Manual U17718EJ1V0UD
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UPD70F3707 arduino
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..............................................430
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Features..................................................................................................................................430
Configuration .........................................................................................................................431
Registers ................................................................................................................................433
Interrupt Request Signals.....................................................................................................439
Operation................................................................................................................................440
12.5.1 Data format.............................................................................................................................. 440
12.5.2 SBF transmission/reception format.......................................................................................... 442
12.5.3 SBF transmission .................................................................................................................... 444
12.5.4 SBF reception.......................................................................................................................... 445
12.5.5 UART transmission.................................................................................................................. 446
12.5.6 Continuous transmission procedure ........................................................................................ 447
12.5.7 UART reception ....................................................................................................................... 449
12.5.8 Reception errors ...................................................................................................................... 450
12.5.9 Parity types and operations ..................................................................................................... 452
12.5.10 Receive data noise filter .......................................................................................................... 453
Dedicated Baud Rate Generator ..........................................................................................454
Cautions .................................................................................................................................462
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................463
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
Features..................................................................................................................................463
Configuration .........................................................................................................................464
Registers ................................................................................................................................466
Interrupt Request Signals.....................................................................................................473
Operation................................................................................................................................474
13.5.1 Single transfer mode (master mode, transmission/reception mode)........................................ 474
13.5.2 Single transfer mode (master mode, reception mode)............................................................. 475
13.5.3 Continuous mode (master mode, transmission/reception mode)............................................. 476
13.5.4 Continuous mode (master mode, reception mode).................................................................. 477
13.5.5 Continuous reception mode (error).......................................................................................... 478
13.5.6 Continuous mode (slave mode, transmission/reception mode) ............................................... 479
13.5.7 Continuous mode (slave mode, reception mode) .................................................................... 480
13.5.8 Clock timing ............................................................................................................................. 481
Output Pin Status with Operation Disabled .......................................................................483
Operation Flow ......................................................................................................................484
Baud Rate Generator ............................................................................................................490
13.8.1 Baud rate generation ............................................................................................................... 491
Cautions .................................................................................................................................492
CHAPTER 14 DMA FUNCTION (DMA CONTROLLER) ....................................................................493
14.1 Features..................................................................................................................................493
14.2 Configuration .........................................................................................................................494
14.3 Registers ................................................................................................................................495
14.4 Transfer Targets ....................................................................................................................503
14.5 Transfer Modes......................................................................................................................503
14.6 Transfer Types.......................................................................................................................504
14.7 DMA Channel Priorities ........................................................................................................505
14.8 Time Related to DMA Transfer.............................................................................................505
Preliminary User’s Manual U17718EJ1V0UD
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