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PDF SC485 Data sheet ( Hoja de datos )
| Número de pieza | SC485 | |
| Descripción | Dual Synchronous Buck | |
| Fabricantes | Semtech | |
| Logotipo |  |
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POWER MANAGEMENT
Description
The SC485 is a dual output constant on-time
synchronous-buck PWM controller intended for use in
notebook computers and graphics cards. Features
include high efficiency and a fast dynamic response with
no minimum on-time. The excellent transient response
means that SC485 based solutions will require less
output capacitance than competing fixed frequency
converters. The two outputs are designed according to
their target role. Output 1 is designed to power IO or
other static rails, whereas output 2 is designed to power
rails requiring dynamic voltage transitioning. Output 2 has
a tighter DC accuracy of 0.85% combined with a higher
OVP threshold of 20% to simplify the design and reduce
component count.
Each output voltage can be independently adjusted from
0.5V to VCCA. Two frequency setting resistors set the
on-time for each buck controller. The frequency can thus
be tailored to minimize crosstalk. The integrated gate
drivers feature adaptive shoot-through protection and
soft switching, requiring no gate resistors for the top
MOSFET. Additional features include cycle-by-cycle current
limit, digital soft-start, over-voltage and under-voltage
protection, and a Power Good output for each controller.
Typical Application Circuit
SC485
Dual Synchronous Buck For
Dynamic Voltage Trwawnw.sDaittaiSoheneti4nU.cgom
Features
Output 1 has 1% DC accuracy and 10% OVP
Output 2 has 0.85% DC accuracy and 20% OVP for
simple dynamic voltage transitioning
Constant on-time for fast dynamic response
Programmable VOUT range = 0.5 – VCCA
VBAT Range = 1.8V – 25V
DC current sense using low-side RDS(ON) sensing
or sense resistor
Resistor programmable on-time
Cycle-by-cycle current limit
Digital soft-start
Separate ENABLE & PSAVE for each switcher
Over-voltage/Under-voltage fault protection
10uA typical shutdown current
Low quiescent power dissipation
Two separate power good indicators
Integrated gate drivers with soft switching - no gate
resistors required
28 pin TSSOP (lead free)
Applications
Graphics cards
Embedded graphics processors
High performance processors
VBAT
5VSUS
5VSUS
PGOOD
R1
RTON1
R5
C5
1nF
R2
10R
VOUT1
R3
R7
C6
1uF
U1
22 EN/PSV1
23 TON1
24 VOUT1
25 VCCA1
26 FB1
27 PGD1
28 VSSA1
SC485
BST1 7
DH1 6
LX1 5
ILIM1 4
VDDP1 3
DL1 2
PGND1 1
D1
C1 0.1uF
R4
C4
1uF
PGOOD
VBAT
VSSA1
5VSUS
R8
RTON2
R9
10R
VOUT2
R10
R12
R14
C11
C12
1nF 1uF
8 EN/PSV2
9 TON2
10 VOUT2
11 VCCA2
12 FB2
13 PGD2
14 VSSA2
5VSUS
BST2 21
DH2 20
LX2 19
ILIM2 18
VDDP2 17
DL2 16
PGND2 15
D2
C7 0.1uF
R11
C10
1uF
VSSA2
VBAT
Q1 C2
10uF
L1
VOUT1
C3
+
Q2 R6 0R
VSSA1
VBAT
Q3 C8
10uF
L2
VOUT2
C9
+
Q4 R13 0R
VSSA2
Revision: February 11, 2005
1
www.semtech.com
1 page  
POWER MANAGEMENT
Pin Configuration
Top View
SC485
Ordering Information
www.DataSheet4U.com
Device
SC485ITSTRT(1)(2)
SC485EVB
Package
TSSOP-28
Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE, RoHS
and J-STD-020B compliant.
TSSOP-28
Pin Descriptions
Pin # Pin Name Pin Function
1 PGND1 Power ground.
2 DL1 Gate drive output for the low side MOSFET switch.
3 VDDP1 +5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to
PGND1.
4 ILIM1 Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for
resistor sensing through a threshold sensing resistor.
5 LX1 Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
6 DH1 Gate drive output for the high side MOSFET switch.
7 BST1 Boost capacitor connection for the high side gate drive.
8 EN/PSV2 Enable/Power Save input. Pull down to VSSA2 to shut down OUT2. Pull up to enable OUT2 and
activate PSAVE mode. Float to enable OUT2 and activate continuous conduction mode (CCM),
which should be used for dynamic voltage transitioning. If floated, bypass to VSSA2 with a 10nF
ceramic capacitor.
9 TON2 This pin is used to sense VBAT through a pullup resistor, RTON2, and to set the top MOSFET on-
time. Bypass this pin with a 1nF ceramic capacitor to VSSA2.
10 VOUT2 Output voltage sense input for output 2. Connect to the output at the load.
11 VCCA2 Supply voltage input for the analog supply. Use a 10 Ohm / 1uF RC filter from 5VSUS to VSSA2.
12 FB2 Feedback input. Connect to a resistor divider located at the IC from VOUT2 to VSSA2 to set the
output voltage from 0.5V to VCCA2.
13 PGD2 Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles)
following power up. An external pull-up resistor is required.
14 VSSA2 Ground reference for analog circuitry. Connect to PGND2 at the bottom of the output capacitor.
2005 Semtech Corp.
5
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5 Page 
SC485
POWER MANAGEMENT
485 System DC Accuracy
Two IC parameters affect system DC accuracy, the error
comparator threshold voltage variation and the switching
frequency variation with line and load. The error
comparator threshold does not drift significantly with
supply and temperature. Thus, the error comparator
contributes 1% (OUT1, 0.85% for OUT2) or less to DC
system inaccuracy.
Board components and layout also influence DC
accuracy. The use of 1% feedback resistors contribute
1%. If tighter DC accuracy is required use 0.1% feedback
resistors.
The on pulse in the SC485 is calculated to give a pseudo
fixed frequency. Nevertheless, some frequency variation
with line and load can be expected. This variation changes
the output ripple voltage. Because constant on regulators
regulate to the valley of the output ripple, ½ of the output
ripple appears as a DC regulation error. For example, if
the feedback resistors are chosen to divide down the
output by a factor of five, the valley of the output ripple
will be VOUT. For example: if VOUT is 2.5V and the ripple
is 50mV with VBAT = 6V, then the measured DC output
will be 2.525V. If the ripple increases to 80mV with VBAT
= 25V, then the measured DC output will be 2.540V.
The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage. It will not change the frequency.
Switching frequency variation with load can be minimized
by choosing MOSFETs with lower RDS(ON). High RDS(ON)
MOSFETs will cause the switching frequency to increase
as the load current increases. This will reduce the ripple
and thus the DC output voltage.
Design Procedure
Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. For purposes
of demonstrating the procedure the output for the
schematic in Figure 8 on Page 17 will be designed.
www.DataSheet4U.com
purposes of this design example we will use a VBAT range
of 8V to 20V and design OUT2. The design for OUT1
employs the same technique.
Four parameters are needed for the output:
1) nominal output voltage, VOUT (we will use 1.2V)
2) static (or DC) tolerance, TOLST (we will use +/-4%)
3) transient tolerance, TOLTR and size of transient (we will
use +/-8% and 6A for purposes of this demonstration).
4) maximum output current, IOUT (we will design for 6A)
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
function of VIN2. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. It is recommended that the two outputs
are designed to operate at frequencies approximately
25% apart to avoid any possible interaction. It is also
recommended that the higher frequency output is the
lower output voltage output, since this will tend to have
lower output ripple and tighter specifications. The
default RtON values of 1MΩ and 715kΩ are suggested
as a starting point, but these are not set in stone. The
first
and
thing to
V ,BAT(MAX)
do is
since
to calculate the on-time,
this depends only upon
VtOBNA,T,aVt OVUBTATa(MnINd)
RtON.
For VOUT < 3.3V:
( )tON_ VBAT(MIN) = 3.3 • 10−12 • RtON + 37 • 103
•
VOUT
VBAT(MIN)
+
50
• 10−9 s
and
( )tON_ VBAT(MAX) = 3.3 • 10−12 •
RtON + 37 • 103
•
VOUT
VBAT ( MAX )
+
50
• 10−9 s
From these values of tON we can calculate the nominal
switching frequency as follows:
( )f =SW _ VBAT(MIN)
VOUT
V • tBAT(MIN) ON _ VBAT(MIN)
Hz
and
The
the
hmigahxiemsut mACinapduatpvtoolrtavgoelt(aVgBeAT.(MTAXh))eismdinetimerummineindpbuyt
voltage (VBAT(MIN)) is determined by the lowest battery
voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches. For the
( )f =SW _ VBAT(MAX)
VOUT
V • tBAT(MAX ) ON _ VBAT(MAX )
Hz
tON is generated by a one-shot comparator that samples
VBAT via RtON, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to VOUT. The
2005 Semtech Corp.
11
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SC485.PDF ] | |
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