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PDF CDC1631F-E Data sheet ( Hoja de datos )
| Número de pieza | CDC1631F-E | |
| Descripción | Automotive Controller | |
| Fabricantes | Micronas | |
| Logotipo |  |
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MICRONAS
ADVANCE INFORMATION
CDC1631F-E
Automotive Controller
Edition June 11, 2003
6251-617-1AI
MICRONAS
1 page  
Table 1–1: CDC16xxF Family Feature List, continued
This Device:
Item
CDC1605F-E
EMU
CDC1607F-E
MCM Flash
CDC1631F-E
MASK ROM
CDC1605F-C
EMU
CDC1607F-C
MCM Flash
Communication
DMA
1 DMA Channel for serving the
Graphics Bus interface
-
1 DMA Channel for serving the
Graphics Bus interface
UART
3: UART0, UART1 and UART2
1: UART0
3: UART0, UART1 and UART2
Synchronous Serial
Peripheral Interfaces
2: SPI0 and SPI1
1: SPI0
2: SPI0 and SPI1
Full CAN modules V2.0B
3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN000F)
1: CAN0 with
256-byte object
RAM
(LCAN000F)
3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN0009)
DIGITbus
1 master module
- 1 master module
Input & Output
Universal Ports select-
able as 4:1 mux LCD
Segment/Backplane lines
or Digital I/O Ports
up to 52 I/O or 48 LCD segment lines (=192 segments),
in groups of two, configurable as I/O or LCD
Universal Port Slew Rate HW preselectable
Stepper Motor Control
Modules with High-Cur-
rent Ports
5 Modules, 24 dI/dt controlled ports
8-bit PWM Modules
5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
3 Modules:
PWM0, PWM1,
PWM2
5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
Audio Module with auto-
decay
SW selectable Clock out- 2
puts
Polling/Flash Timer Out- 1 High-Current Port output operable in Power Saving -
put Mode
CDC1641F-C
Mask ROM
CDC1652F-C
Mask ROM
CDC1672F-C
Mask ROM
-
1: UART0
1: SPI0
1 DMA Channel for serving the
Graphics Bus interface
3: UART0, UART1 and UART2
2: SPI0 and SPI1
1: CAN0 with
256-byte object
RAM
(LCAN0009)
2: CAN0 and CAN1 with 256-byte
object RAM each (LCAN0009)
- 1 master module
2 Modules:
5 Modules: PWM0, PWM1,
PWM0, PWM1 PWM2, PWM3 and PWM4
5 Page 
ADVANCE INFORMATION
2.3. External Components
+5 V
C = 100 n to 150 n
L
C
18 p
C
+5 V
4.7 k
Resetq
System
Ground
18 p
47 n
CDC1631F-E
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UVDD
C = 100 n to 150 n
VDD
VSS HVDD 0 to 1
XTAL1
HVSS 0 to 1
IC
AVDD
+5 V
2*C
System
Ground
+5 V Analog
XTAL2
RESETQ
VREF
AVSS
10 n
UVSS
C
Analog
Ground
Fig. 2–2: Recommended external supply and quartz connection for low electromagnetic interference (EMI)
To provide effective decoupling and to improve EMC behav-
ior, the small decoupling capacitors must be located as close
to the supply pins as possible. The self-inductance of these
capacitors and the parasitic inductance and capacitance of
the interconnecting traces determine the self-resonant fre-
quency of the decoupling network. A frequency too low will
reduce decoupling effectiveness, increase RF emissions and
may affect device operation adversely.
XTAL1 and XTAL2 quartz connections are especially sensi-
tive to capacitive coupling from other printed circuit board
signals. It is strongly recommended to place quartz and
oscillation capacitors as close to the pins as possible and to
shield the XTAL1 and XTAL2 traces from other signals by
embedding them in a VSS trace.
The RESETQ pin adjacent to XTAL2 should be supplied with
a 47 nF capacitor, to prevent fast RESETQ transients from
being coupled into XTAL2, to prevent XTAL2 from coupling
into RESETQ, and to guarantee a time constant of ≥ 200 µs,
sufficient for proper Wake Reset functionality.
Micronas
June 11, 2003; 6251-617-1AI
11
11 Page | ||
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